View ADT7462ACPZ-500RL7_6223269.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

flexible temperature and voltage monitor and system fan controller adt7462 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006C2007 analog devices, inc. all rights reserved. features one local and up to three remote temperature channels series resistance cancellation on remote channels thermal protection using therm pins up to four pwm fan drive outputs supports both high and low frequency pwm drives up to eight tach inputs measures the speed of 3-wire and 4-wire fans automatic fan speed control loop includes dynamic t min control monitors up to 13 voltage inputs monitors up to 7 vid inputs includes vid-on-fly support bidirectional reset chassis intrusion detect smbus 1.1 and smbus 1.0 compatible 3.3 v and 5 v operation extended operating range from ?40c to +125c space-saving 32-lead chip scale package applications servers and personal computers telecommunications equipment test equipment and measurement instruments general description the adt7462 is a flexible systems monitor ic, suitable for use in a wide variety of applications. it can monitor temperature in up to three remote locations, as well as its ambient temperature. there are up to four pwm outputs. these can be used to control the speed of a cooling fan by varying the % duty cycle of the pwm drive signal applied to the fan. the adt7462 supports high frequency pwm for 4-wire fans and low frequency pwm for 2-wire and 3-wire fans. up to eight tach inputs can be used to measure the speed of 3-wire and 4-wire fans. there are up to 13 voltage monitoring inputs, ranging from 12 v to 0.9 v. the adt7462 is fully compatible with smbus 1.1 and smbus 1.0. the adt7462 also includes a therm i/o and a reset i/o. the adt7462 is available in a 32-lead lfcsp_vq. many of the pins are multifunctional. five easy configuration options can be set up using the easy configuration register. users choose the configuration closest to their requirements; individual pins can be reconfigured after the easy configuration option has been chosen. functional block diagram smbus address selection serial bus interface vid register pwm registers address pointer register pwm configuration registers interrupt masking reset circuit gpio status and configuration registers scsi status performance monitoring thermal protection input signal conditioning and analog multiplexer band gap temperature sensor vid0 to vid6 pwm1 to pwm4 tach1 to tach8 vr_hot2 scsi_term1 and scsi_term2 vr_hot1 therm2 thermal diode inputs voltage inputs adt7462 value and limit registers limit comparators interrupt status registers automatic fan speed control acoustic enhancement control dynamic t min control 13-bit adc band gap reference gpio1 to gpio8 reset ci gnd add scl sda alert fan speed counter 05569-001 fan2max therm1 figure 1.
adt7462 rev. a | page 2 of 92 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications..................................................................................... 3 timing diagram ........................................................................... 4 absolute maximum ratings............................................................ 5 thermal resistance ...................................................................... 5 esd caution.................................................................................. 5 pin configuration and function descriptions............................. 6 function description: easy configuration options ............... 9 typical performance characteristics ........................................... 14 serial bus interface......................................................................... 17 add input................................................................................... 17 smbus fixed address ................................................................ 17 smbus operation ....................................................................... 17 write operations ........................................................................ 19 read operations ......................................................................... 20 alert response address............................................................. 21 smbus timeout .......................................................................... 21 temperature and voltage measurement...................................... 22 temperature measurement ....................................................... 22 series resistance cancellation.................................................. 23 voltage measurement ................................................................ 25 battery measurement input (v batt )......................................... 27 adc information....................................................................... 27 dynamic vid functionality ......................................................... 29 vid code .................................................................................... 29 dynamic vid monitoring ........................................................ 29 status and mask registers and alert........................................ 31 status registers ........................................................................... 31 alert output............................................................................ 31 mask registers ............................................................................ 31 fan control...................................................................................... 32 fan drive using pwm control ............................................... 32 fan speed measurement and control ......................................... 34 tach inputs............................................................................... 34 fan speed measurement ........................................................... 34 pwm logic state........................................................................ 37 fan speed control...................................................................... 37 programming the automatic fan speed control loop........ 38 step 1configuring the mux ................................................ 39 step 2t min settings for thermal calibration channels .... 39 step 3pwm min for each pwm (fan) output .................... 41 step 4pwm max for pwm (fan) outputs............................ 41 step 5t range for temperature channels.............................. 42 step 6t therm for temperature channels ............................. 45 step 7t hyst for temperature channels................................ 46 step 8operating points for temperature channels........... 48 step 9high and low limits for temperature channels ... 48 step 10monitoring therm ................................................. 51 enhancing system acoustics .................................................... 51 step 11ramp rate for acoustic enhancement................... 53 fan freewheeling test mode .................................................... 55 therm i/o operation ................................................................. 56 therm output.......................................................................... 56 therm input............................................................................. 56 therm timer ........................................................................... 57 general-purpose i/o pins............................................................. 58 edo circuitry ............................................................................ 58 other digital inputs................................................................... 59 reset i/o...................................................................................... 59 chassis intrusion input ............................................................. 59 power-up sequence ....................................................................... 60 xor tree test ................................................................................. 61 register map ................................................................................... 62 outline dimensions ....................................................................... 89 ordering guide .......................................................................... 89 revision history 10/07rev. 0 to rev. a changes to table 4............................................................................ 6 changes to configuration option 3 section .............................. 11 changes to figure 22...................................................................... 16 changes to figure 37...................................................................... 25 changes to battery measurement input (v batt ) ........................ 27 changes to fan speed measurement section............................. 34 changes to table 26 ....................................................................... 36 1/06revision 0: initial version
adt7462 rev. a | page 3 of 92 specifications t a = t min to t max , v cc = v min to v max , unless otherwise noted. 1 table 1. parameter min typ max unit test conditions/comments power supply supply voltage 3.0 3.3 5.5 v supply current 1.5 4 ma adc active, interface inactive 2 temperature-to-digital converter t a conditions v cc conditions internal sensor, t a , accuracy 0.5 2.25 c 0c t a 85c 3 v v cc 3.6 v 0.5 3.25 c ?40c t a +100c 3 v v cc 3.6 v 0.5 3 c 0c t a 85c 4.5 v v cc 5.5 v 0.5 4 c ?40c t a +100c 4.5 v v cc 5.5 v resolution 0.25 c remote sensor, t d , accuracy (?40c t d +125c) 0.5 2.25 c 0c t a 85c 3 v v cc 3.6 v 0.5 3.25 c ?40c t a +100c 3 v v cc 3.6 v 0.5 2.75 c 0c t a 85c 4.5 v v cc 5.5 v 0.5 3.5 c ?40c t a +100c 4.5 v v cc 5.5 v resolution 0.25 c remote sensor source current 3 85 a high level 34 a mid level 5 a low level series resistance cancellation 3 2 k the adt7462 cancels 2 k in series with the remote thermal diode analog-to-digital converter total unadjusted error, tue 4, 5 3.5 % differential nonlinearity, dnl 1 lsb 8 bits conversion time (voltage input) 3 8.53 9.86 ms conversion time (local temperature) 3 9.01 10.38 ms conversion time (remote temperature) 3 38.36 42.09 ms input resistance pin 7, pin 8, pin 13, pin 21, pin 22, pin 25, pin 28, pin 29 140 k attenuators enabled pin 15, pin 19 225 k attenuators enabled pin 23, pin 24 66 k attenuators enabled pin 26, v batt and +1.2v2 (when measured) 100 120 140 k attenuators cannot be disabled v batt current drain (when measured) 80 100 na cr2032 battery life > 10 years v batt current drain (when not measured) 16 na cr2032 battery life > 10 years fan rpm to digital converter accuracy 8 % internal clock frequency 82.8 90 97.2 khz open-drain outputs (pwm, gpio) high level output leakage current, i oh 0.1 1 a v out = v cc output low voltage, v ol 0.4 v i out = ?3 ma, v cc = +3.3 v digital output (reset , alert , therm ) output low voltage, v ol 0.4 v i out = ?3 ma, v cc = +3.3 v reset pulse width 3 140 180 ms reset threshold 3 3.05 3.1 v falling voltage reset hysteresis 3 70 mv open-drain serial bus output (sda) output low voltage, v ol 0.4 v i out = ?3 ma, v cc = +3.3 v high level output leakage current, i oh 0.1 1 a v out = v cc
adt7462 rev. a | page 4 of 92 parameter min typ max unit test conditions/comments serial bus digital inputs (sda and scl) input high voltage, v ih 2.1 v input low voltage, v il 0.4 v hysteresis 500 mv digital input logic levels (vid0 to vid6) and therm , tach, gpio, vr_hot, scsi_term) input high voltage, v ih 1.7 v bit 3 and bit 4 of configuration register 3 = 0 input low voltage, v il 0.8 v bit 3 and bit 4 of configuration register 3 = 0 input high voltage, v ih (vid0 to vid6) 0.65 v bit 3 of configuration register 3 = 1 input high voltage, v ih (therm ) 2/3 v ccp1 v bit 4 of configuration register 3 = 1 input low voltage, v il 0.4 v bit 3 and bit 4 of configuration register 3 = 1 hysteresis 500 mv digital input currents input high current, i ih ?1 a v in = v cc input low current, i il +1 a v in = 0 input capacitance 3 5 pf serial bus timing 3 clock frequency 400 khz see figure 2 glitch immunity, t sw 50 ns see figure 2 bus free time 1.3 s see figure 2 start setup time, t su;sta 0.6 s see figure 2 start hold time, t hd;sta 0.6 s see figure 2 scl low time, t low 1.3 s see figure 2 scl high time, t high 0.6 s see figure 2 scl, sda rise time, t r 1000 ns see figure 2 scl, sda fall time, t f 300 ns see figure 2 data setup time, t su;dat 100 ns see figure 2 detect clock low timeout 25 ms can be optionally enabled 1 all voltages are measured with respect to gnd, unless otherwise specified. typical values are at t a = 25c and represent the most likely parametric norm. logic inputs accept input high voltages up to 5 v, even when the device is operating at supply vo ltages below 5 v. timing specifications are tested at logic levels of v il = 0.8 v for a falling edge and v ih = 2.0 v for a rising edge. 2 unused digital inputs connected to gnd. 3 guaranteed by design, not production tested. 4 note that this specification does not apply if pin 26 (v batt , +1.2v) is being measured in single-channel mode. see figure 22 in the typical performance characteristics section for v batt accuracy. 5 for pin 23 and pin 24 configured as +1.8v or +2.5v only, restrict ed conditions of v cc 3.3 v and +25c t a +125c apply. timing diagram scl sda ps s p t su;sto t hd;sta t su;sta t su;dat t hd;dat t hd;sta t high t buf t low t r t f 05569-002 figure 2. serial bus timing diagram
adt7462 rev. a | page 5 of 92 absolute maximum ratings table 2. parameter rating supply voltage 6.5 v voltage on +12v pin 20 v voltage on v batt pin 4 v voltage on any other input or output pin ?0.3 v to +6.5 v input current at any pin 5 ma package input current 20 ma maximum junction temperature 150c operating temperature range ?40c to +125c storage temperature range ?65c to +150c lead temperature (soldering, 10 sec) 300c ir reflow peak temperature 260c esd rating 1500 v stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 3. thermal resistance package type ja jc unit 32-lead lfcsp_vq 32.5 32.71 c/w esd caution
adt7462 rev. a | page 6 of 92 pin configuration and fu nction descriptions pin 1 indicator 1 v id0/gpio1/tach1 2 v id1/gpio2/tach2 3 v id2/gpio3/tach3 4 v id3/gpio4/tach4 5 v cc 6 gnd 7 tach5/+12v1 8 tach6/+12v2 24 v ccp2 /+1.5v/+1.8v/+2.5v 23 v ccp1 /+1.5v/+1.8v/+2.5v 22 tach8/+12v3 21 tach7/+5v 20 d3?/scsi_term2 19 d3+/+1.25v/+0.9v 18 d2? 17 d2+ 9 s c l 1 0 s d a 1 1 a d d 1 2 a l e r t 1 3 p w m 4 / + 3 . 3 v 1 4 r e s e t 1 5 d 1 + / + 2 . 5 v / + 1 . 8 v 1 6 d 1 ? / s c s i _ t e r m 1 3 2 v i d 5 / g p i o 6 / p w m 2 3 1 v i d 4 / g p i o 5 / p w m 1 3 0 p w m 3 2 9 t h e r m 2 / + 1 . 5 v 2 / g p i o 8 2 8 t h e r m 1 / + 1 . 5 v 1 / g p i o 7 / v i d 6 2 7 f a n 2 m a x / c i 2 6 v r _ h o t 2 / + 1 . 2 v 2 / v b a t t 2 5 adt7462 top view (not to scale) 0 5569-009 v r _ h o t 1 / + 1 . 2 v 1 / + 3 . 3 v figure 3. pin configuration table 4. pin function descriptions pin no. mnemonic description por default 1 vid0/gpio1/tach1 vid0: digital input (open drain). voltage supply readouts from cpu. this value is read in to the vid value register (0x97). tach1 gpio1: open-drain i/o. ge neral-purpose input/output. tach1: digital input (open drain). fan tachometer input to measure speed of fan 1. 2 vid1/gpio2/tach2 vid1: digital input (open drain). voltage supply readouts from cpu. this value is read in to the vid value register (0x97). tach2 gpio2: open-drain i/o. ge neral-purpose input/output. tach2: digital input (open drain). fan tachometer input to measure speed of fan 2. 3 vid2/gpio3/tach3 vid2: digital input (open drain). voltage supply readouts from cpu. this value is read in to the vid value register (0x97). tach3 gpio3: open-drain i/o. ge neral-purpose input/output. tach3: digital input (open drain). fan tachometer input to measure speed of fan 3. 4 vid3/gpio4/tach4 vid3: digital input (open drain). voltage supply readouts from cpu. this value is read in to the vid value register (0x97). tach4 gpio4: open-drain i/o. ge neral-purpose input/output. tach4: digital input (open drain). fan tachometer input to measure speed of fan 4. 5 v cc power supply. can be powered by 3.3 v standby if monitoring in low power states is required. the adt7462 can also be powered from a 5 v supply. v cc 6 gnd ground pin. gnd 7 tach5/+12v1 tach5: digital input (open drain). fan tachometer input to measure speed of fan 5. tach5 +12v1: analog input. monitors 12 v power supply 1. attenuators switched on by default. 8 tach6/+12v2 tach6: digital input (open drain). fan tachometer input to measure speed of fan 6. tach6 +12v2: analog input. monitors 12 v power supply 2. attenuators switched on by default.
adt7462 rev. a | page 7 of 92 pin no. mnemonic description por default 9 scl digital input (open drain). smbus serial clock input. requires smbus pull-up. scl 10 sda digital i/o (open drain). smbus bidirectional serial data. requires smbus pull- up. sda 11 add the state of this pin on power-up determines the smbus device address. add 12 alert active low open-drain digital output. requires 10 k typical pull-up. the alert pin is used to signal out-of-limit comparisons of temperature, voltage, and fan speed. this is compatible with smbus alert. alert 13 pwm4/+3.3v pwm4: digital output (open drain). requires 10 k typical pull-up. pulse- width modulated output to control the speed of fan 4. pwm4 +3.3v: analog input. monitors 3.3 v power supply. 14 reset active low open-drain digital i/o. power-on reset, 5 ma driver (weak 100 k pull-up), active low output (100 k pull-up) with a 180 ms typical pulse width. reset is asserted whenever v cc is below the reset threshold. it remains asserted for approximately 180 ms after v cc rises above the reset threshold. pin 14 also functions as an active low reset input and resets all unlocked registers to their default values. reset 15 d1+/+2.5v/+1.8v d1+: anode connection to thermal diode 1. d1+ +2.5v: monitors 2.5 v analog input. +1.8v: monitors 1.8 v analog input. 16 d1?/scsi_term1 d1?: cathode conne ction to thermal diode 1. d1? scsi_term1: digital input, scsi termination 1. 17 d2+ anode connection to thermal diode 2. d2+ 18 d2? cathode connection to thermal diode 2. d2? 19 d3+/+1.25v/+0.9v d3+: anode connection to thermal diode 3. d3+ +1.25v: monitors 1.25 v analog input. +0.9v: monitors 0.9 v analog input. 20 d3?/scsi_term2 d3?: cathode conne ction to thermal diode 3. d3? scsi_term2: digital input, scsi termination 2. 21 tach7/+5v tach7: digital input (open drain). fan tachometer input to measure speed of fan 7. tach7 +5v: analog input. monitors 5 v power supply. 22 tach8/+12v3 tach8: digital input (open drain). fan tachometer input to measure speed of fan 8. tach8 +12v3: analog input. monitors 12 v power supply 3. 23 v ccp1 /+1.5v/+1.8v/+2.5v v ccp1 : monitors 1.2 v analog input. +1.8v +1.5v: monitors 1.5 v analog input. +1.8v: monitors 1.8 v analog input. +2.5v: monitors 2.5 v analog input. 24 v ccp2 /+1.5v/+1.8v/+2.5v v ccp2 : monitors 1.2 v analog input. +2.5v +1.5v: monitors 1.5 v analog input. +1.8v: monitors 1.8 v analog input. +2.5v: monitors 2.5 v analog input. 25 vr_hot1/+1.2v1/+3.3v vr_hot1: digital input indicating overtemperature event on voltage regulator. +3.3v +1.2v1: 0 v to 1.2 v analog input. for example, can be used to monitor g bit . +3.3v: analog input. monitors 3.3 v power supply. 26 vr_hot2/+1.2v2/v batt vr_hot2: digital input indicating overtemperature event on voltage regulator. v batt +1.2v2: 0 v to 1.2 v analog input. fo r example, can be used to monitor fsb_v tt . v batt : analog input. monitors battery voltage, nominally 3 v. 27 fan2max /ci fan2max : sets fan to maximum speed when a fan fault condition occurs. bidirectional open drain, active low i/o. ci ci: an active high input that captures a chassis intrusion event in bit 7 of the digital status register. this bit remains set until cleared, as long as battery voltage is applied to the v batt input, even when the adt7462 is powered off.
adt7462 rev. a | page 8 of 92 pin no. mnemonic description por default 28 therm1 /+1.5v1/gpio7/vid6 therm1 : can be reconfigured as a bidirectional therm pin. can be connected to the prochot output of the intel? pentium? 4 processor to time and monitor prochot assertions. can be used as an output to signal overtemperature conditions or for clock modulation purposes. therm1 +1.5v1: 0 v to 1.5 v analog input. can be used to monitor ich. gpio7: open-drain i/o. ge neral-purpose input/output. vid6: digital input (open drain). voltage supply readouts from cpu. this value is read in to the vid value register (0x97). 29 therm2 /+1.5v2/gpio8 therm2 : can be reconfigured as a bidirectional therm pin. can be connected to the prochot output of the intel pentium 4 processor to time and monitor prochot assertions. can be used as an output to signal overtemperature conditions or for clock modulation purposes. therm2 +1.5v2: 0 v to 1.5 v analog input. can be used to monitor 3gio. gpio8: open-drain i/o. ge neral-purpose input/output. 30 pwm3 digital output (open drain). requires 10 k typical pull-up. pulse-width modulated output to control the speed of fan 3. pwm3 31 vid4/gpio5/pwm1 vid4: digital input (open drain). voltage supply readouts from cpu. this value is read in to the vid value register (0x97). pwm1 gpio5: open-drain i/o. ge neral-purpose input/output. pwm1: digital output (open drain). requires 10 k typical pull-up. pulse- width modulated output to control the speed of fan 1. 32 vid5/gpio6/pwm2 vid5: digital input (open drain). voltage supply readouts from cpu. this value is read in to the vid value register (0x97). pwm2 gpio6: open-drain i/o. ge neral-purpose input/output. pwm2: digital output (open drain). requires 10 k typical pull-up. pulse- width modulated output to control the speed of fan 2.
adt7462 rev. a | page 9 of 92 function description: easy configuration options there are a number of multifunctional pins on the adt7462 that need to be configured on power-up to suit the desired application. note that due to the large number of pins that need to be configured, it could take several smbus transactions to achieve the required configuration. for this reason, the adt7462 has five easy configuration options. the user sets a bit in the easy configuration option register (0x14) to set up the required configuration (see table 5). table 5. easy configuration register settings easy configuration option register 0x14 setting option 1 bit 0 = 1 option 2 bit 1 = 1 option 3 bit 2 = 1 option 4 bit 3 = 1 option 5 bit 4 = 1 once the most convenient easy configuration option has been set, the user can configure any of the pins individually. the setup complete bit (bit 5 of register 0x01) must then be set to 1 to indicate that the adt7462 is configured correctly, and then monitoring of the selected channels begins. the following is a detailed description of the five easy configuration options that are available. configuration option 1 configuration option 1 is the default configuration. it is also the most suitable for thermal monitoring, voltage monitoring, and fan control for single and dual processor systems. features of configuration option 1 include the following: ? one local and three remote temperature channels ? four pwm drives and eight tach inputs ? two therm i/os ? volt age monitor ing ? +3.3v ? +2.5v ? +1.8v ? v batt ? reset i/o ? ci (chassis intrusion) or fan2max figure 4 shows the pin configuration when configuration option 1 is chosen. pin 1 indicator 1 t ach1 2 t ach2 3 t ach3 4 t ach4 5 v cc 6 gnd 7 t ach5 8 t ach6 24 +2.5v 23 +1.8v 22 tach8 21 tach7 20 d3? 19 d3+ 18 d2? 17 d2+ 9 s c l 1 0 s d a 1 1 a d d 1 2 a l e r t 1 3 p w m 4 1 4 r e s e t 1 5 d 1 + 1 6 d 1 ? 3 2 p w m 2 3 1 p w m 1 3 0 p w m 3 2 9 t h e r m 2 2 8 t h e r m 1 2 7 c i 2 6 v b a t t 2 5 + 3 . 3 v adt7462 top view (not to scale) 05569-010 figure 4. configuration option 1 table 6. configuration option 1 pin function configuration register bit value 1 1 tach1 pin configuration register 1 bit 4 = 1 2 1 tach2 pin configuration register 1 bit 3 = 1 3 1 tach3 pin configuration register 1 bit 2 = 1 4 1 tach4 pin configuration register 1 bit 1 = 1 7 tach5 pin configuration register 1 bit 0 = 1 8 tach6 pin configuration register 2 bit 7 = 1 13 pwm4 pin configuration register 2 bit 6 = 1 15 d1+ pin configuration register 1 bit 6 = 1 16 d1? pin configuration register 1 bit 6 = 1 19 d3+ pin configuration register 1 bit 5 = 1 20 d3? pin configuration register 1 bit 5 = 1 21 tach7 pin configuration register 2 bit 3 = 1 22 tach8 pin configuration register 2 bit 2 = 1 23 +1.8v pin configuration register 2 bits [1:0] = 10 24 +2.5v pin configuration register 3 bits [7:6] = 01 25 +3.3v pin configuration register 3 bits [5:4] = 00 26 v batt pin configuration register 3 bits [3:2] = 00 27 ci pin configuration register 3 bit 1 = 1 28 1 therm1 pin configuration register 4 bits [7:6] = 1 29 therm2 pin configuration register 4 bits [5:4] = 1 31 1 pwm1 pin configuration register 4 bit 3 = 1 32 1 pwm2 pin configuration register 4 bit 2 = 1 1 if vids are selected, these pins are co nfigured as vids. to enable vids, set bit 7 of pin configuration register 1 (0x10) = 1.
adt7462 rev. a | page 10 of 92 configuration option 2 configuration option 2 is used for thermal monitoring and fan control for processor 1 and processor 2 in a dual processor system. it can also monitor one set of vids, if required. features of configuration option 2 include the following: ? one local and three remote thermal channels ? up to four pwm drives and up to eight tach inputs (vid pins and tachs/pwms are muxed together) ? two therm i/os ? two vrd inputs ? reset i/o ? two v ccp voltage monitoring channels figure 5 shows the pin configuration when configuration option 2 is chosen. pin 1 indicator 1 t ach1 2 t ach2 3 t ach3 4 t ach4 5 v cc 6 gnd 7 t ach5 8 t ach6 24 v ccp2 23 v ccp1 22 tach8 21 tach7 20 d3? 19 d3+ 18 d2? 17 d2+ 9 s c l 1 0 s d a 1 1 a d d 1 2 a l e r t 1 3 p w m 4 1 4 r e s e t 1 5 d 1 + 1 6 d 1 ? 3 2 p w m 2 3 1 p w m 1 3 0 p w m 3 2 9 t h e r m 2 2 8 t h e r m 1 2 7 f a n 2 m a x 2 6 v r _ h o t 2 2 5 v r _ h o t 1 adt7462 top view (not to scale) 05569-011 figure 5. configuration option 2 table 7. configuration option 2 pin function configuration register bit value 1 1 tach1 pin configuration register 1 bit 4 = 1 2 1 tach2 pin configuration register 1 bit 3 = 1 3 1 tach3 pin configuration register 1 bit 2 = 1 4 1 tach4 pin configuration register 1 bit 1 = 1 7 tach5 pin configuration register 1 bit 0 = 1 8 tach6 pin configuration register 2 bit 7 = 1 13 pwm4 pin configuration register 2 bit 6 = 1 15 d1+ pin configuration register 1 bit 6 = 1 16 d1? pin configuration register 1 bit 6 = 1 19 d3+ pin configuration register 1 bit 5 = 1 20 d3? pin configuration register 1 bit 5 = 1 21 tach7 pin configuration register 2 bit 3 = 1 22 tach8 pin configuration register 2 bit 2 = 1 23 v ccp1 pin configuration register 2 bits [1:0] = 00 24 v ccp2 pin configuration register 3 bits [7:6] = 00 25 vr_hot1 pin configuration register 3 bits [5:4] = 1 26 vr_hot2 pin configuration register 3 bits [3:2] = 1 27 fan2max pin configuration register 3 bit 1 = 0 28 1 therm1 pin configuration register 4 bits [7:6] = 1 29 therm2 pin configuration register 4 bits [5:4] = 1 31 1 pwm1 pin configuration register 4 bit 3 = 1 32 1 pwm2 pin configuration register 4 bit 2 = 1 1 if vids are selected, these pins are configured as vids. to enable vids, set bit 7 of pin configuration register 1 (0x01) = 1.
adt7462 rev. a | page 11 of 92 configuration option 3 configuration option 3 is used to monitor all the voltages in the system for processor 1 and processor 2. additional pins can be configured for fan control, vids, or gpios, as required. features of configuration option 3 include the following: ? up to 13 different voltages monitored ? three +12v ? +5v ? +3.3v ? +2.5v ? +1.8v ? two +1.5v ? two +1.2v (v ccp1 , v ccp2 ) ? 0.9v ? v batt ? one local and one remote temperature channels ? up to three pwm drives and up to four tach inputs ? reset i/o figure 6 shows the pin configuration when configuration option 3 is chosen. pin 1 indicator 1 tach1 2 tach2 3 tach3 4 tach4 5 v cc 6 gnd 7 +12v1 8 +12v2 24 v ccp2 23 v ccp1 22 +12v3 21 +5v 20 scsi_term2 19 +0.9v 18 d2? 17 d2+ 9 s c l 1 0 s d a 1 1 a d d 1 2 a l e r t 1 3 + 3 . 3 v 1 4 r e s e t 1 5 + 1 . 8 v 1 6 s c s i _ t e r m 1 3 2 p w m 2 3 1 p w m 1 3 0 p w m 3 2 9 + 1 . 5 v / g p i o 8 2 8 + 1 . 5 v / g p i o 7 2 7 c i 2 6 v b a t t 2 5 + 1 . 2 v adt7462 top view (not to scale) 0 5569-012 figure 6. configuration option 3 table 8. configuration option 3 pin function configuration register bit value 1 1 tach1 pin configuration register 1 bit 4 = 1 2 1 tach2 pin configuration register 1 bit 3 = 1 3 1 tach3 pin configuration register 1 bit 2 = 1 4 1 tach4 pin configuration register 1 bit 1 = 1 7 +12v1 pin configuration register 1 bit 0 = 0 8 +12v2 pin configuration register 2 bit 7 = 0 13 +3.3v pin configuration register 2 bit 6 = 0 15 +1.8v pin configuration register 1 bit 6 = 0 16 scsi_term1 pin configuration register 1 bit 6 = 0 19 +0.9v pin configuration register 1 bit 5 = 0 20 scsi_term2 pin configuration register 1 bit 5 = 0 21 +5v pin configuration register 2 bit 3 = 0 22 +12v3 pin configuration register 2 bit 2 = 0 23 v ccp1 pin configuration register 2 bits [1:0] = 00 24 v ccp2 pin configuration register 3 bits [7:6] = 00 25 +1.2v pin configuration register 3 bits [5:4] = 01 26 v batt pin configuration register 3 bits [3:2] = 00 27 ci pin configuration register 3 bit 1 = 1 28 1 +1.5v/gpio7 pin configuration register 4 bits [7:6] = 01 29 +1.5v/gpio8 pin configuration register 4 bits [5:4] = 01 31 1 pwm1 pin configuration register 4 bit 3 = 1 32 1 pwm2 pin configuration register 4 bit 2 = 1 1 if vids are selected, these pins are co nfigured as vids. to enable vids, set bit 7 of pin configuration register 1 (0x01) = 1.
adt7462 rev. a | page 12 of 92 configuration option 4 configuration option 4 is used to monitor temperature, voltages, and fans for processor 1 in a dual processor system. features of configuration option 4 include the following: ? one local and two remote temperature channels ? up to four pwm drives and six tach inputs ? up to eight voltages monitored ? +12v ? +5v ? +3.3v ? two +1.5v ? +1.2v (v ccp1 ) ? +0.984v (mem_v tt ) ? v batt ? therm i/o ? vrd input ? reset i/o figure 7 shows the pin configuration when configuration option 4 is chosen. pin 1 indicator 1 tach1 2 tach2 3 tach3 4 tach4 5 6 7 tach5 8 tach6 24 +2.5v 23 v ccp1 22 +12v3 21 +5v 20 scsi_term2 19 +0.9v 18 17 9 1 0 1 1 1 2 1 3 p w m 4 1 4 1 5 d 1 + 1 6 d 1 ? 3 2 p w m 2 3 1 p w m 1 3 0 2 9 t h e r m 2 / + 1 . 5 v 2 8 t h e r m 1 / + 1 . 5 v 2 7 f a n 2 m a x 2 6 v b a t t 2 5 v r _ h o t 1 adt7462 top view (not to scale) v cc gnd d2? d2+ s c l s d a a d d a l e r t r e s e t p w m 3 05569-013 figure 7. configuration option 4 table 9. configuration option 4 pin function configuration register bit value 1 1 tach1 pin configuration register 1 bit 4 = 1 2 1 tach2 pin configuration register 1 bit 3 = 1 3 1 tach3 pin configuration register 1 bit 2 = 1 4 1 tach4 pin configuration register 1 bit 1 = 1 7 tach5 pin configuration register 1 bit 0 = 1 8 tach6 pin configuration register 2 bit 7 = 1 13 pwm4 pin configuration register 2 bit 6 = 1 15 d1+ pin configuration register 1 bit 6 = 1 16 d1? pin configuration register 1 bit 6 = 1 19 +0.9v pin configuration register 1 bit 5 = 0 20 scsi_term2 pin configuration register 1 bit 5 = 0 21 +5v pin configuration register 2 bit 3 = 0 22 +12v3 pin configuration register 2 bit 2 = 0 23 v ccp1 pin configuration register 2 bits [1:0] = 00 24 +2.5v pin configuration register 3 bits [7:6] = 01 25 vr_hot1 pin configuration register 3 bits [5:4] = 1 26 v batt pin configuration register 3 bits [3:2] = 00 27 fan2max pin configuration register 3 bit 1 = 0 28 1, 2 therm1 / +1.5v pin configuration register 4 see table 51 29 2 therm2 / +1.5v pin configuration register 4 see table 51 31 1 pwm1 pin configuration register 4 bit 3 = 1 32 1 pwm2 pin configuration register 4 bit 2 = 1 1 if vids are selected, these pins are co nfigured as vids. to enable vids, set bit 7 of pin configuration register 1 (0x01) = 1. 2 it is not possible to configure +1.5v monitoring on pin 29 and therm1 on pin 28. pin 28 and pin 29 must both be configured as either +1.5v moni- toring or as therm i/o (see table 51).
adt7462 rev. a | page 13 of 92 configuration option 5 configuration option 5 is used to monitor temperature, voltages, and fans for processor 2 in a dual processor system. features of configuration option 5 include the following: ? one local and two remote temperature channels ? up to three pwm drives and up to six tach inputs ? volt age monitor ing ? two +12v ? +3.3v ? mem_core (+1.969v) ? +1.8 v ? two +1.5v ? +1.2v (v ccp2 ) ? reset i/o figure 8 shows the pin configuration when configuration option 5 is chosen. t h e r m 2 / + 1 . 5 v t h e r m 1 / + 1 . 5 v pin 1 indicator 1 t ach1 2 t ach2 3 t ach3 4 t ach4 5 6 7 +12v1 8 +12v2 24 v ccp2 23 +1.8v 22 tach8 21 tach7 20 d3? 19 d3+ 18 17 9 1 0 1 1 1 2 1 3 + 3 . 3 v 1 4 1 5 + 2 . 5 v 1 6 s c s i _ t e r m 1 3 2 p w m 2 3 1 p w m 1 3 0 2 9 2 8 2 7 f a n 2 m a x 2 6 v r _ h o t 2 2 5 + 1 . 2 v adt7462 top view (not to scale) v cc gnd d2? d2+ s c l s d a a d d a l e r t r e s e t p w m 3 0 5569-014 figure 8. configuration option 5 table 10. configuration option 5 pin function configuration register bit value 1 1 tach1 pin configuration register 1 bit 4 = 1 2 1 tach2 pin configuration register 1 bit 3 = 1 3 1 tach3 pin configuration register 1 bit 2 = 1 4 1 tach4 pin configuration register 1 bit 1 = 1 7 +12v1 pin configuration register 1 bit 0 = 0 8 +12v2 pin configuration register 2 bit 7 = 0 13 +3.3v pin configuration register 2 bit 6 = 0 15 +2.5v pin configuration register 1 bit 6 = 0 16 scsi_term1 pin configuration register 1 bit 6 = 0 19 d3+ pin configuration register 1 bit 5 = 1 20 d3? pin configuration register 1 bit 5 = 1 21 tach7 pin configuration register 2 bit 3 = 1 22 tach8 pin configuration register 2 bit 2 = 1 23 +1.8v pin configuration register 2 bits [1:0] = 10 24 v ccp2 pin configuration register 3 bits [7:6] = 00 25 +1.2v pin configuration register 3 bits [5:4] = 01 26 vr_hot2 pin configuration register 3 bits [3:2] = 1 27 fan2max pin configuration register 3 bit 1 = 0 28 1, 2 therm1 / +1.5v pin configuration register 4 see table 51 29 2 therm2 / +1.5v pin configuration register 4 see table 51 31 1 pwm1 pin configuration register 4 bit 3 = 1 32 1 pwm2 pin configuration register 4 bit 2 = 1 1 if vids are selected, these pins are co nfigured as vids. to enable vids, set bit 7 of pin configuration register 1 (0x01) = 1. 2 it is not possible to configure +1.5v monitoring on pin 28 and therm2 on pin 29. pin 28 and pin 29 must both be configured as either +1.5v monitoring or as therm i/o (see table 51).
adt7462 rev. a | page 14 of 92 typical performance characteristics 0.00160 0.00125 2.9 3.4 3.9 4.4 4.9 5.4 05569-003 supply voltage (v) i dd (amps) dev1 dev2 dev3 0.00155 0.00150 0.00145 0.00140 0.00135 0.00130 figure 9. supply current vs. supply voltage 0.00144 0.00122 ?45 5 55 105 05569-004 temperature (c) i dd (amps) 0.00142 0.00140 0.00138 0.00136 0.00134 0.00132 0.00130 0.00128 0.00126 0.00124 dev1 dev2 dev3 figure 10. supply current vs. temperature 2 ?1 ?40 ?20 0 20 40 60 80 100 120 05569-005 temperature (c) temperature error (c) 1 0 v cc =5.5v v cc =3.3v figure 11. local sensor temperature error 2 ?1 ?40 ?20 0 20 40 60 80 100 120 05569-006 temperature (c) temperature error (c) 1 0 v cc = 3.3v v cc = 5.5v figure 12. remote sensor temperature error 5 ?4 ?40 ?20 0 20 40 60 80 100 120 05569-007 temperature (c) temperature error (c) 4 3 2 1 0 ?1 ?2 ?3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 mean lo spec hi spec figure 13. temperature error measuring intel pentium 4 processor 140 0 0120 05569-008 time (seconds) temperature reading (c) 120 100 80 60 40 20 20 40 60 80 100 int ext1 ext2 ext3 figure 14. adt7462 response to thermal shock
adt7462 rev. a | page 15 of 92 60 ?60 0100 05569-077 resistance (m ? ) temperature error (c) 40 20 0 ?20 ?40 20 40 60 80 d+ to gnd d+ to v cc figure 15. remote temperature error vs. resistance (src) 15 ?20 10 1g 05569-078 power supply noise frequency (khz) temperature error (c) 100 1m 10m 100m 10 5 0 ?5 ?10 ?15 50mv 125mv figure 16. local temperature error vs. power supply noise frequency 8 ?12 10 1g 05569-079 power supply noise frequency (khz) temperature error (c) 100 1m 10m 100m 50mv 125mv 6 4 2 0 ?2 ?4 ?6 ?8 ?10 figure 17. remote temperature error vs. power supply noise frequency 25 ?10 10 1g 05569-080 noise frequency (khz) temperature error (c) 100 1m 10m 100m 20 15 10 5 0 ?5 100mv 60mv 40mv figure 18. remote temperature error vs. common-mode noise frequency 7 ?1 10 1g 05569-081 noise frequency (khz) temperature error (c) 100 1m 10m 100m 6 5 4 3 2 1 0 10mv 20mv figure 19. remote temperature error vs. differential-mode noise frequency 10 ?50 010 05569-082 capacitance (nf) temperature error (c) 0 ?10 ?20 ?30 ?40 2468 dev1, ext1 dev1, ext2 dev1, ext3 dev2, ext1 dev2, ext2 dev2, ext3 dev3, ext1 dev3, ext2 dev3, ext3 figure 20. remote temperature error vs. capacitance between d+ and d?
adt7462 rev. a | page 16 of 92 0.200 0.180 ?50 150 05569-083 timeout (seconds) temperature (c) 0.198 0.196 0.194 0.192 0.190 0.188 0.186 0.184 0.182 0 50 100 power up standby figure 21. local temperature vs. power-on reset timeout 3.0 0 03.0 05569-084 v batt reading (v) voltage applied to v batt (v) 2.5 2.0 1.5 1.0 0.5 0.5 1.0 1.5 2.0 2.5 dev1 dev2 dev3 figure 22. applied voltage vs. v batt reading 5.0 0 2.9 3.4 3.9 4.4 4.9 5.4 05569-085 supply (v) tach error (%) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 dev1 dev2 dev3 figure 23. tach accuracy vs. supply voltage 1.5 ?2.0 ?50 150 05569-086 temperature (c) tach error (%) 1.0 0.5 0 ?0.5 ?1.0 ?1.5 0 50 100 dev1 dev2 dev3 figure 24. tach accuracy vs. temperature
adt7462 rev. a | page 17 of 92 serial bus interface the adt7462 is controlled through use of the serial system management bus (smbus). the adt7462 is connected to this bus as a slave device, under the control of a master controller. the smbus interface in the adt7462 is fully smbus 1.1 and smbus 1.0 compliant. the smbus address is determined by the state of the add input on power-up. add input the add pin is a three-state input to the adt7462. it is used to determine the smbus address used. this pin is sampled on power-up only. any changes subsequent to power-up are not reflected until the adt7462 is powered down and back up again. the corresponding 7-bit smbus address for the state of the add pin is shown in table 11. table 11. corresponding smbus addresses for add input add pin smbus version smbus address high n/a n/a float smbus 1.1 0x5c low smbus 1.1 0x58 smbus fixed address the adt7462 supports smbus fixed address mode and is fully backward compatible with smbus 1.1 and smbus 1.0. the adt7462 powers up with a fixed smbus address that cannot be changed by the assign address call. the fixed address is set by the state of the add input pin on power-up. the adt7462 also responds to the smbus device default address of 0x61. smbus operation the smbus specification defines specific conditions for different types of read and write operations. the general smbus protocol operates as follows: 1. the master initiates data transfer by establishing a start condi- tion, defined as a high-to-low transition on the serial data line, sda, while the serial clock line, scl, remains high. this indicates that an address/data stream follows. all slave peripherals connected to the serial bus respond to the start condition and shift in the next eight bits, consisting of a 7-bit address (msb first) plus a r/ w bit, which determines the direction of the data transfer, that is, whether data is written to or read from the slave device. 2. the peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the 9th clock pulse, known as the acknowledge bit. all other devices on the bus remain idle while the selected device waits for data to be read from it or written to it. if the r/ w bit = 0, the master writes to the slave device. if the r/ w bit = 1, the master reads from the slave device. 3. data is sent over the serial bus in sequences of nine clock pulses: eight bits of data followed by an acknowledge bit from the slave device. transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-to-high transition when the clock is high can be interpreted as a stop signal. the number of data bytes that can be transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle. 4. when all data bytes have been read or written, stop conditions are established. in write mode, the master releases the data line during the 10th clock pulse to assert a stop condition. in read mode, the master device overrides the acknowledge bit by pulling the data line high during the low period before the 9th clock pulse. this is known as a no acknowledge. the master then takes the data line low during the low period before the 10th clock pulse and then takes it high during the 10th clock pulse to assert a stop condition. any number of bytes of data can be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation. for the adt7462, write operations contain either one or two bytes, and read operations contain one byte. to write data to one of the device data registers or to read data from it, the address pointer register must be set so that the correct data register is addressed. then data can be written into that register or read from it. the first byte of a write operation always con- tains an address that is stored in the address pointer register. if data is to be written to the device, the write operation contains a second data byte that is written to the register selected by the address pointer register. this write operation is shown in figure 25. the device address is sent over the bus, and then r/ w is set to 0. this is followed by two data bytes. the first data byte is the address of the internal data register to be written to, which is stored in the address pointer register. the second data byte is the data to be written to the internal data register.
adt7462 rev. a | page 18 of 92 when reading data from a register, there are two possibilities. ? if the adt7462 address pointer register value is unknown or not the desired value, it must be set to the correct value before data can be read from the desired data register. this is done by performing a write to the adt7462 as before, but only the data byte containing the register address is sent because no data is written to the register (see figure 26). a read operation is then performed, consisting of the serial bus address and the r/ w bit set to 1, followed by the data byte read from the data register (see figure 27). ? if the address pointer register is known to be already at the desired address, data can be read from the corresponding data register without first writing to the address pointer register (see figure 27). it is possible to read a data byte from a data register without first writing to the address pointer register, if the address pointer register is already at the correct value. however, it is not possible to write data to a register without writing to the address pointer register, because the first data byte of a write is always written to the address pointer register. in addition to supporting the send byte and receive byte protocols, the adt7462 also supports the read byte protocol (see system management bus specifications rev. 2.0 for more information). if several read or write operations must be performed in succession, then the master can send a repeat start condition, instead of a stop condition, to begin a new operation. a3 scl sda start by master ack. by adt7462 ack. by adt7462 ack. by adt7462 stop by master frame 2 address pointer register byte frame 1 serial bus address byte 19 19 9 1 r/w d7 d6 d5 d4 d3 d2 d1 d0 a6 a5 a4 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 scl (continued) sda (continued) frame 3 data byte 05569-015 figure 25. writing a register address to the address pointe r register, then writing data to the selected register a3 scl sda start by master ack. by adt7462 ack. by adt7462 stop by master frame 2 address pointer register byte frame 1 serial bus address byte 19 9 1 r/w d7 d6 d5 d4 d3 d2 d1 d0 a6 a5 a4 a2 a1 a0 0 5569-016 figure 26. writing to the address pointer register only a3 scl sda start by master ack. by adt7462 no ack. by master stop by master frame 2 data byte from adt7462 frame 1 serial bus address byte 19 9 1 r/w d7 d6 d5 d4 d3 d2 d1 d0 a6 a5 a4 a2 a1 a0 0 5569-017 figure 27. reading data from a previously selected register
adt7462 rev. a | page 19 of 92 write operations the smbus specification defines several protocols for different types of read and write operations. the ones used in the adt7462 are discussed below. the following abbreviations are used in the diagrams: ? s C start ? p C stop ? r C read ? w C write ? a C acknowledge ? a C no acknowledge the adt7462 uses the following smbus write protocols. send byte in this operation, the master device sends a single command byte to a slave device as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts an ack on sda. 4. the master sends a command code. 5. the slave asserts an ack on sda. 6. the master asserts a stop condition on sda to end the transaction. for the adt7462, the send byte protocol is used to write a register address to ram for a subsequent single byte read from the same address. this operation is shown in figure 28. slave address register address swa ap 24 1356 05569-018 figure 28. setting a register address for a subsequent read if it is required to read data from the register immediately after setting up the address, the master can assert a repeat start condition immediately after the final ack and carry out a single byte read without asserting an intermediate stop condition. write byte in this operation, the master device sends a command byte and one data byte to the slave device as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts an ack on sda. 4. the master sends a command code. 5. the slave asserts an ack on sda. 6. the master sends a data byte. 7. the slave asserts an ack on sda. 8. the master asserts a stop condition on sda to end the transaction. slave address slave address swa data ap a 24 1358 7 6 05569-019 figure 29. single byte write to a register block write in this operation, the master device writes a block of data to a slave device. the start address for a block write must be set previously. in the case of the adt7462, this is done by a send byte operation to set a ram address. the user writes the number of registers to be written to in the block read command to the #bytes bits of the configuration 0 register. 1. the master device asserts a start condition on the sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts an ack on the sda. 4. the master sends a command code that tells the slave device to expect a block write. the adt7462 command code for a block write is 0xa0 (1010 0000). 5. the slave asserts an ack on sda. 6. the master sends the data bytes (the number of data bytes sent is written to the #bytes bits of the configuration 0 register). 7. the slave asserts an ack on sda after each data byte. 8. the master sends a packet error checking (pec) byte. 9. the adt7462 checks the pec byte and issues an ack, if correct. if incorrect (no ack), the master resends the data bytes. 10. the master asserts a stop condition on sda to end the transaction. swa a adata 1 aa ap data 2 a data 32 pec slave address command 0xa0 block write byte count 12 3 4 56789 101112 05569-020 figure 30. block write to adt7462
adt7462 rev. a | page 20 of 92 read operations the adt7462 uses the following smbus read protocols. receive byte the receive byte is useful when repeatedly reading a single register. the register address must be set up previously. in this operation, the master device receives a single byte from a slave device as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the read bit (high). 3. the addressed slave device asserts an ack on sda. 4. the master receives a data byte. 5. the master asserts a no ack on sda. 6. the master asserts a stop condition on sda to end the transaction. for the adt7462, the receive byte protocol is used to read a single byte of data from a register whose address has previously been set by a send byte or write a byte operation. 23 146 5 slave address srdatap a a 05569-021 figure 31. single byte read from a register block read in this operation, the master device reads a block of data from a slave device. the start address for a block read must be set previously, as well as the number of bytes to be read (maximum = 32). in the case of the adt7462, the start address is activated by a send byte operation to set a ram address. the number of bytes to be read should be written to the #bytes bits in the configuration 0 register. the block read operation consists of a send byte operation that sends a block read command to the slave, immediately followed by a repeated start and a read operation that reads out multiple data bytes, as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts an ack on sda. 4. the master sends a command code that tells the slave device to expect a block read. the adt7462 command code for a block read is 0xa1 (1010 0001). 5. the slave asserts an ack on sda. 6. the master asserts a repeat start condition on sda. 7. the master sends the 7-bit slave address followed by the read bit (high). 8. the slave asserts an ack on sda. 9. the adt7462 sends a byte count telling the master how many data bytes to expect. the maximum number of bytes is 32. 10. the master asserts an ack on sda. 11. the master receives the expected number of data bytes. 12. the master asserts an ack on sda after each data byte. 13. the adt7462 issues a pec byte to the master. the master should check the pec byte and issue another block read if the pec byte is incorrect. 14. a no ack is generated after the pec byte to signal the end of the read. 15. the master asserts a stop condition on sda to end the transaction. s slave address wa command 0xa1 block read a s r ap data 32 pec a byte count a data 1 a slave address a 1 8 9 10 12 13 14 15 11 234567 05569-022 figure 32. block read from ram note that although the adt7462 supports packet error checking (pec), its use is optional. the pec byte is calculated using crc-8. the frame check sequence (fcs) conforms to crc-8 by the polynomial () 1 1 2 8 + + + = consult the smbus 1.1 specifications for more information.
adt7462 rev. a | page 21 of 92 alert response address alert response address (ara) is a feature of smbus devices that allows an interrupting device to identify itself to the host when multiple devices exist on the same bus. the smbalert output can be used as either an interrupt output or an smbalert . one or more outputs can be connected to a common smbalert line connected to the master. if a devices smbalert line goes low, the following procedure occurs: 1. smbalert is pulled low. 2. the master initiates a read operation and sends the alert response address (ara = 0001 100). this is a general call address that must not be used as a specific device address. 3. the device whose smbalert output is low responds to the alert response address, and the master reads its device address. the address of the device is now known and can be interrogated in the usual way. 4. if more than one devices smbalert output is low, the one with the lowest device address has priority in accordance with normal smbus arbitration. 5. once the adt7462 has responded to the alert response address, the master must read the status registers, and the smbalert is cleared only if the error condition has gone away. smbus timeout the adt7462 includes an smbus timeout feature. if there is no smbus activity for 25 ms, the adt7462 assumes that the bus is locked and releases the bus. this prevents the device from locking or holding the smbus while the device is expecting data. some smbus controllers cannot handle the smbus time- out feature, so it can be disabled. configuration register 3 (0x03) bit 1 scl_timeout = 1; scl timeout enabled. bit 1 scl_timeout = 0; scl timeout disabled (default). bit 2 sda_timeout = 1; sda timeout enabled. bit 2 sda_timeout = 0; sda timeout disabled (default).
adt7462 rev. a | page 22 of 92 temperature and voltage measurement temperature measurement the adt7462 can measure its own ambient temperature and the temperature of up to three remote thermal diodes. these diodes can be discrete diode-connected 2n3904/2n3906s or they can be located on a processor die. figure 33 shows how to connect a remote npn or pnp transistor. d+ d? adt7462 2n3904 d+ d? adt7462 2 n3906 05569-023 figure 33. how to measure temperature using discrete transistors remote thermal diode 1 connects to pin 15 and pin 16. remote thermal diode 2 connects to pin 17 and pin 18. remote thermal diode 3 connects to pin 19 and pin 20. a simple method of measuring temperature is to exploit the negative temperature coefficient of a diode, measuring the base- emitter voltage (v be ) of a transistor, operated at constant current. unfortunately, this technique requires calibration to cancel the effect of the absolute value of v be , which varies from device to device. the technique used in the adt7462 is to measure the change in v be when the device is operated at three different currents. previous devices have used only two operating currents; use of a third current allows automatic cancellation of any resistances in series with the external temperature sensor. figure 34 shows the input signal conditioning used to measure the output of an external temperature sensor. this figure shows the external sensor as a substrate transistor, but it could equally be a discrete transistor. if a discrete transistor is used, the collector is not grounded and should be linked to the base. to prevent ground noise from interfering with the measurement, the more negative terminal of the sensor is not referenced to ground but is biased above ground by an internal diode at the d? input. c1 can optionally be added as a noise filter (recommended maximum value 1000 pf). however, a better option in noisy environments is to add a filter, as described in the noise filtering section. to me asure v be , the operating current through the sensor is switched among three related currents. as shown in figure 34, n1 i and n2 i are different multiples of the current i. the currents through the temperature diode are switched between i and n1 i, giving v be1 , and then between i and n2 i, giving v be2 . the temperature can then be calculated using the two v be measurements. this method can also be shown to cancel the effect of any series resistance on the temperature measurement. the resulting v be waveforms are passed through a 65 khz low-pass filter to remove noise and then to a chopper-stabilized amplifier. this amplifies and rectifies the waveform to produce a dc voltage proportional to v be . the adc digitizes this voltage, and a temperature measurement is produced. to reduce the effects of noise, digital filtering is performed by averaging the results of 16 measurement cycles for low conversion rates. signal conditioning and measurement of the internal tempera- ture sensor are performed in the same manner (see figure 34). temperature measurement results the results of the local and remote temperature measurements are stored in the local and remote temperature value registers and are compared with limits programmed into the local and remote high and low limit registers. table 12. temperature measurement registers temperature value register address local temperature, lsb register 0x88, bits [7:6] local temperature, msb register 0x89 remote 1 temperature, lsb register 0x8a, bits [7:6] remote 1 temperature, msb register 0x8b remote 2 temperature, lsb register 0x8c, bits [7:6] remote 2 temperature, msb register 0x8d remote 3 temperature, lsb register 0x8e, bits [7:6] remote 3 temperature, msb register 0x8f c1* d+ bias diode *capacitor c1 is optional. it should only be used in noisy environments. v cc to adc v out+ v out? remote sensing transistor d? i n1 i n2 i i bias low-pass filter f c = 65khz 05569-024 figure 34. input signal conditioning
adt7462 rev. a | page 23 of 92 the temperature value is stored in two registers. the msb has a resolution of 1c. only two bits in the temperature lsb register are used, bit 7 and bit 6, giving a temperature measurement resolution of 0.25c. the temperature measurement range for both local and remote measurements is from ?64c to +191c. however, the adt7462 itself should never be operated outside its operating temperature range, which is from ?40c to +125c. for the remote diode, the user should refer to the data sheet of the diode. table 13. temperature data format temperature value msb lsb ?64c 0000 0000 0000 0000 ?50.25c 0000 1110 0100 0000 ?25c 0010 0111 0000 0000 0c 0100 0000 0000 0000 +25c 0101 1001 0000 0000 +50.25c 0111 0010 0100 0000 +100c 1010 0100 0000 0000 when reading the full temperature value, the lsb should be read first and then the msb. reading the lsbs causes the current msbs to be frozen until they are read. reading the msbs only does not cause any register to be locked. this is useful when a temperature reading with 1c resolution is required. series resistance cancellation parasitic resistance in series with the remote diode d+ and d? inputs can be caused by a variety of factors, including pcb track resistance and track length. this series resistance appears as a temperature offset in the remote sensors temperature measure- ment. this error typically causes a 0.8c offset per ohm of parasitic resistance in series with the remote diode. the adt7462 automatically cancels out the effect of this series resistance on the temperature reading, giving a more accurate result, without the need for user characterization of this resistance. the adt7462 is designed to automatically cancel typically up to 2 k of resistance. by using an advanced temperature measurement method, the process is transparent to the user. this feature also allows an rcr filter to be added to the sensor path, allowing the part to be used accurately in noisy environments. temperature limits each temperature measurement channel has a high and low temperature limit associated with it. the temperature measure- ments are compared with these limits, and the results of these comparisons are stored in status registers. a logic 0 indicates an in-limit comparison, and a logic 1 indicates an out-of-limit comparison. the adt7462 can generate an alert , if configured to do so, after a status bit is set. for more information on the status registers and alert , see the status and mask registers and alert section. each temperature channel also has a therm1 and a therm2 temperature limit associated with it. when these temperature limits are exceeded, the corresponding therm pin is asserted low (if therm is configured as an output), and the fans are boosted to full speed (if the boost bit is set). table 14 shows a complete list of all the temperature limits and their default values. table 14. temperature limit registers temperature value register address default local low temperature limit 0x44 0x40 remote 1 low temperature limit 0x45 0x40 remote 2 low temperature limit 0x46 0x40 remote 3 low temperature limit 0x47 0x40 local high temperature limit 0x48 0x95 remote 1 high temperature limit 0x49 0x95 remote 2 high temperature limit 0x4a 0x95 remote 3 high temperature limit 0x4b 0x95 local therm1 temperature limit 0x4c 0xa4 remote 1 therm1 temperature limit 0x4d 0xa4 remote 2 therm1 temperature limit 0x4e 0xa4 remote 3 therm1 temperature limit 0x4f 0xa4 local therm2 temperature limit 0x50 0xa4 remote 1 therm2 temperature limit 0x51 0xa4 remote 2 therm2 temperature limit 0x52 0xa4 remote 3 therm2 temperature limit 0x53 0xa4 offset registers the adt7462 has temperature offset registers at register 0x56 to register 0x59 for the local, remote 1, remote 2, and remote 3 temperature channels. by doing a one-time calibration of the system, the user can determine the offset caused by system board noise and cancel it using the offset registers. the offset registers automatically add a twos complement, 8-bit reading to every temperature measurement. the lsbs add 0.5c offset to the temperature reading so the 8-bit register effectively allows temperature offsets of up to 64c with a resolution of 0.5c. this ensures that the readings in the temperature measurement registers are as accurate as possible. temperature offset registers register 0x56 local temperature offset = 0x00 (0c default) register 0x57 remote 1 temperature offset = 0x00 (0c default) register 0x58 remote 2 temperature offset = 0x00 (0c default) register 0x59 remote 3 temperature offset = 0x00 (0c default)
adt7462 rev. a | page 24 of 92 layout considerations digital boards can be electrically noisy environments. the adt7462 measures very small voltages from the remote sensor, so care must be taken to minimize noise induced at the sensor inputs. the following precautions should be taken: ? place the adt7462 as close as possible to the remote sensing diode. provided that the worst noise sources, such as clock generators, data/address buses, and crts, are avoided, this distance can be 4 inches to 8 inches. ? route the d+ and d? tracks close together, in parallel, with grounded guard tracks on each side. to minimize inductance and reduce noise pickup, a 5 mil track width and spacing is recommended. if possible, provide a ground plane under the tracks. 5mil 5mil 5mil 5mil 5mil 5mil 5mil gnd d+ gnd d? 0 5569-025 figure 35. typical arrangement of signal tracks ? minimize the number of copper/solder joints that can cause thermocouple effects. where copper/solder joints are used, make sure that they are in both the d+ and d? path and at the same temperature. ? thermocouple effects should not be a major problem because 1c corresponds to about 200 mv, and thermocouple voltages are about 3 mv/c of temperature difference. unless there are two thermocouples with a large tempera- ture differential between them, thermocouple voltages should be much less than 200 mv. ? place a 0.1 f bypass capacitor close to the v cc pin. in extremely noisy environments, an input filter capacitor can be placed across d+ and d? close to the adt7462. this capacitance can affect the temperature measurement, so care must be taken to ensure that any capacitance seen at d+ and d? is a maximum of 1000 pf. this maximum value includes the filter capacitance, plus any cable or stray capacitance between the pins and the sensor diode. ? if the distance to the remote sensor is more than 8 inches, the use of twisted pair cable is recommended. this works from about 6 feet up to 12 feet. ? for really long distances (up to 100 feet), use shielded twisted pair, such as belden no. 8451 microphone cable. connect the twisted pair to d+ and d? and the shield to gnd close to the adt7462. leave the remote end of the shield unconnected to avoid ground loops. ? because the measurement technique uses switched current sources, excessive cable or filter capacitance can affect the measurement. when using long cables, the filter capaci- tance can be reduced or removed. noise filtering for temperature sensors operating in noisy environments, the industry-standard practice is to place a capacitor across the d+ and d? pins to help combat the effects of noise. however, large capacitances affect the accuracy of the temperature measure- ment, leading to a recommended maximum capacitor value of 1000 pf. while this capacitor does reduce noise, it does not eliminate it, making it difficult to use the sensor in a very noisy environment. the adt7462 has a major advantage over other devices in eliminating the effects of noise on the external sensor. the series resistance cancellation feature allows a filter to be constructed between the external temperature sensor and the device. the effect of any filter resistance seen in series with the remote sensor is automatically cancelled from the temperature result. the construction of a filter allows the adt7462 and the remote temperature sensor to operate in noisy environments. figure 36 shows a low-pass rcr filter, with the following values: r = 100 c = 1 nf this filtering reduces both common-mode noise and differential noise. 100 ? 100 ? 1nf remote sensor 05569-026 d+ d? figure 36. filter between remo te sensor and the adt7462
adt7462 rev. a | page 25 of 92 voltage measurement the adt7462 is capable of measuring up to 13 different voltage inputs at one time. table 15 is a list of the voltage measurement inputs and the corresponding input pins. each pin can be configured to measure the desired voltage option using the pin configuration 1 (0x10) to pin configuration 4 (0x13) registers or the easy configuration options. table 15. voltage inputs pin voltage measured 7 +12v1 8 +12v2 13 +3.3v 15 +2.5v/+1.8v 19 +1.25v/+0.9v 21 +5v 22 +12v3 23 v ccp1 /+1.5v/+1.8v/+2.5v 24 v ccp2 /+1.5v/+1.8v/+2.5v 25 +1.2v1 (g bit )/+3.3v 26 +1.2v2 (fsb_v tt )/v batt 28 +1.5v1 (ich) 29 +1.5v2 (3gio) input circuit the internal structure for the voltage inputs is shown in figure 37. each input circuit consists of an input protection diode, an attenuator, plus a capacitor to form a first-order, low-pass filter that gives the input immunity to high frequency noise. voltages with full-scale values greater than the reference are divided so that the full-scale value equals the reference (2.25 v). all analog inputs are multiplexed into the on-chip, successive approximation adc. this adc has a resolution of ten bits. the basic input range is from 0 v to 2.25 v, but the inputs have built-in attenuators to allow measurement of larger and smaller voltages. to allow a tolerance for these voltages, the adc produces an output of ? full scale (decimal 768 or 0x300) for the nominal input voltage and so has enough headroom to cope with overvoltages. 0.9v 8k ? 92k ? 35pf 1.25v 30k ? 72k ? 10pf 32k ? 77k ? 10pf 51k ? 66k ? 8pf 1.8v 8k ? 91k ? 35pf 2.5v 30k ? 72k ? 10pf 3.3v 68k ? 71k ? 5pf 5v 76k ? 39k ? 5pf 12v 100k ? 16k ? 5pf mux g bit , fsb_ v tt , v ccp1 , v ccp2 ich, 3gio, 1.5v 05569-027 figure 37. voltage input structures
adt7462 rev. a | page 26 of 92 a list of corresponding lsb and full-scale values for each input voltage is shown in table 16. table 16. input range code conversion nominal input voltage (? scale) pin no. 1 lsb value full scale +12v 7, 8, 22 0.0625 16 v +5v 21 0.026 6.67 v v ccp1 , v ccp2 23, 24 0.00625 1.6 v v ccp1 , when vids are enabled 23 0.0125 3.2 v +3.3v 13, 25 0.0172 4.4 v v batt 26 0.0156 4 v +2.5v 15, 23, 24 0.013 3.33 v +1.8v 15, 23, 24 0.0094 2.4 v +1.5v 23, 24, 28, 29 0.0078 2 v +1.25v 19 0.0065 1.667 v +1.2v 25, 26 0.00625 1.6 v +0.9v 19 0.00469 1.2 v example calculations given the lsb value for each channel, the corresponding code for each voltage (or vice versa) can be calculated. lsb voltage code 1 = example the code for 1.8 v in a 1.8 v channel is 192 0094 . 0 8 . 1 = = (that is, ? scale) similarly, the voltage, given the code in a particular channel, is calculated as follows: voltage = code 1 lsb where: 10 v is connected to the 12 v channel. 1 lsb = 0.0625. code = 160 decimal. voltage measurement and limit registers the corresponding register locations for voltage measurements are listed in table 17. each voltage measurement channel has a high and low voltage limit associated with it. the voltage measurements are compared with these limits. the results of these comparisons are stored in status registers. a logic 0 indicates an in-limit condition, and a logic 1 indicates an out- of-limit condition. the adt7462 can generate an alert , if configured to do so, when a status bit is set. for more informa- tion on the status registers and alert , see the status and mask registers and alert section. a complete list of all the high and low voltage limits in the adt7462 and their default values is contained in table 17. table 17. voltage value and limit registers low limit high limit voltage value pin no. value register address register default register default +12v1 7 0xa3 0x6d 0x00 0x7c 0xff +12v2 8 0xa5 0x6e 0x00 0x7d 0xff +3.3v 13 0x96 0x70 0x00 0x68 0xff +1.8v or +2.5v 15 0x8b 0x45 0x40 0x49 0x95 +1.25v or +0.9v 19 0x8f 0x47 0x40 0x4b 0x95 +5v 21 0xa7 0x71 0x00 0x7e 0xff +12v3 22 0xa9 0x6f 0x00 0x7f 0xff v ccp1 , +1.5v, +1.8v, +2.5v 23 0x90 0x72 0x20 0x69 0xff v ccp2 , +1.5v, +1.8v, +2.5v 24 0x91 0x73 0x00 0x6a 0xff +1.2v1 (g bit ) or +3.3v 25 0x92 0x74 0x00 0x6b 0xff +1.2v2 (fsb_v tt ) or v batt 26 0x93 0x75 0x80 0x6c 0xff +1.5v1 (ich) 28 0x94 0x76 0x00 0x50 0xa4 +1.5v2 (3gio) 29 0x95 0x77 0x00 0x4c 0xa4
adt7462 rev. a | page 27 of 92 battery measurement input (v batt ) the v batt input allows the condition of a cmos backup battery to be monitored. this is typically a lithium coin cell, such as a cr2032. the v batt input is accurate only for voltages greater than 1.2 v. note that when pin 26 is configured as a +1.2v input, voltages lower than 1.2 v are not accurately measured. input voltage and corresponding voltage measured are shown in figure 22. typically, the battery in a system is required to keep some devices powered on when the system is in a powered-off state. the v batt measurement input is designed to minimize battery drain. to reduce current drain from the battery, the lower resistor of the v batt attenuator is not connected, except when a v batt measurement is being made. the total current drain on the v batt pin is 80 na typical (for a maximum v batt voltage = 4 v), so a cr2032 cmos battery functions in a system in excess of the expected 10 years. note that when a v batt measurement is not being made, the current drain is reduced to 16 na typical. under normal voltage measurement operating conditions, all measurements are made in a round-robin format, and each reading is actually the result of 16 digitally averaged measurements. however, averaging is not carried out on the v batt measurement to reduce measurement time and, therefore, reduce the current drain from the battery. the v batt current drain when a measurement is being made is calculated by period pulse batt t t v i = k 100 where: t pulse is the v batt measurement time (~711 s typical). t period is the time required to measure all analog inputs. monitoring cycle time depends on the adt7462 configuration. calculating the monitoring cycle time is described in more detail in the adc information section. v batt input battery protection in addition to minimizing battery current drain, the v batt measurement circuitry is specifically designed with battery protection in mind. internal circuitry prevents the battery from being back-biased by the adt7462 supply or through any other path under normal operating conditions. in the unlikely event of a catastrophic adt7462 failure, the adt7462 includes a second level of battery protection, including a series 3 k resistor to limit current to the battery, as recommended by ul (see figure 38). thus, it is not necessary to add a series resistor between the battery and the v batt input; the battery can be connected directly to the v batt input to improve voltage measurement accuracy. 05569-028 adc v batt digital control 49.5k ? 82.7k ? 4 .5pf 3k ? 3k ? figure 38. equivalent v batt input protection circuit adc information round robin both temperature and voltage measurements are analog inputs that are digitized using the on-board adc. an internal multiplexer switches between the different analog inputs and digitizes them, in turn, in a round-robin manner. the total conversion time depends upon how the adt7462 is configured. the conversion times for each measurement channel are shown in table 18. the complete conversion time is the sum of the time for the voltage and temperature measurements. for example, if the adt7462 is configured as easy configuration option 1, the round-robin conversion time is calculated as follows: total conversion time = 1 ( local conversion time ) + 3 ( remote conversion time ) + 4 ( voltage measurement time ) the tach is not measured using the adc and so is not part of the round-robin monitoring cycle. table 18. measurement channel conversion times channel conversion time (ms) local temperature 9.01 remote temperature 38.36 voltage 8.53 for each adc temperature and voltage measurement read from their value registers, 16 readings have actually been made internally and the results averaged before being placed in the value register. bypass voltage attenuators there are up to 13 voltage measurement channels on the adt7462. each of these voltage measurement channels has an input structure (see figure 37 for input structures for each of the voltage channels). because the adc has a voltage input range from 0 v to 2.25 v, these input circuits attenuate the voltage input using a resistor divider network to match the input range of the adc. however, the user may occasionally want to remove the attenuators and directly apply a voltage of between 0 v and 2.25 v to the adc. these attenuators can be disabled by setting relevant bits in the voltage attenuator configuration registers (see table 19). this feature also allows the user to rescale the voltage inputs using an external attenu- ator circuit. however, when the attenuators are disabled, the user should ensure that the voltage on the pin never exceeds 2.25 v.
adt7462 rev. a | page 28 of 92 table 19. voltage attenuator configuration registers register name register address voltage attenuator configuration register 1 0x18 voltage attenuator configuration register 2 0x19 single-channel adc conversions setting bit 2 of the edo enable register (0x16) places the adt7462 into single-channel mode. in this mode, the adt7462 can be made to convert on a single voltage or temperature channel only. the channel to be converted on is selected by writing to bits [7:3] of the edo (single-channel) enable register (0x16). when the device is in single-channel mode, the pin configuration option should not be changed. note that when the pin 26 voltage, which includes the v batt option, is selected in single-channel mode, this means that voltage measurements are continuously made in this mode. if a battery is connected to this input, this results in an excessive current drain on the battery. the specification of >10 years of battery life is valid only when the battery voltage is measured as part of the round robin and not in single-channel mode. table 20. single-channel mode options bits [7:3] adc channel selected 0000 0 +1.2v2 voltage, pin 26 0000 1 remote 1 temperature 0001 0 remote 2 temperature 0001 1 remote 3 temperature 0010 0 local temperature 0010 1 +12v1 voltage, pin 7 0011 0 +12v2 voltage, pin 8 0011 1 +12v3 voltage, pin 22 0100 0 +3.3v voltage, pin 13 0100 1 +2.5v/+1.8v voltage, pin 15 0101 0 +1.25v/+0.9v voltage, pin 19 0101 1 +5v voltage, pin 21 0110 0 +1.5v/+1.8v/+2.5v voltage, pin 23 0110 1 +1.5v/+1.8v/+2.5v voltage, pin 24 0111 0 +1.2v1/+3.3v voltage, pin 25 1000 0 +1.5v1 voltage, pin 28 1000 1 +1.5v2 voltage, pin 29
adt7462 rev. a | page 29 of 92 dynamic vid functionality vid code the adt7462 can be configured to monitor up to seven vid inputs. the vid code is output on seven lines from the cpu to tell the power controller what input voltage it requires. the adt7462 can monitor the vid code and the voltage applied to the cpu to ensure that they match within an acceptable range. this acceptable range is programmable in the adt7462. the vid lines are monitored by the adt7462, and the vid code is stored in the vid value register (0x97), which can be read back over the smbus. vid monitoring is enabled by setting bit 7 (vids) of pin configuration register 1 (0x10) to 1. see table 21 and table 22 for information on which pin should be connected to each vid line. when vid monitoring is enabled, all seven pins are automatically configured as vid inputs. it is not possible to select six pins as vid inputs and use the remaining pin as an alternate function. vid value register (0x97) bit 0 = vid0 (reflects the logic state of pin 1) bit 1 = vid1 (reflects the logic state of pin 2) bit 2 = vid2 (reflects the logic state of pin 3) bit 3 = vid3 (reflects the logic state of pin 4) bit 4 = vid4 (reflects the logic state of pin 31) bit 5 = vid5 (reflects the logic state of pin 32) bit 6 = vid6 (reflects the logic state of pin 28) the adt7462 supports both the vr10 and the vr11 specifica- tions. the default option supports the vr10 specification. to switch to the vr11 specification, set bit 6 of configuration register 0 (0x00) to 1. vr11 is defined as eight bits; the adt7462 monitors only seven vid lines (see table 21). table 21. vr11 vid codes vid number pin no. voltage vid6 28 400 mv vid5 32 200 mv vid4 31 100 mv vid3 4 50 mv vid2 3 25 mv vid1 2 12.5 mv vid0 1 6.25 mv vr10 requires only six vid lines (see table 22). pin 28 should be connected to ground when monitoring vr10 vid codes. vid6 reports a 0. table 22. vr10 vid codes vid number pin no. voltage vid6 28 unused, connect to gnd vid5 32 12.5 mv vid4 31 400 mv vid3 4 200 mv vid2 3 100 mv vid1 2 60 mv vid0 1 25 mv dynamic vid monitoring the adt7462 supports dynamic vid monitoring. the purpose of the vid code is to tell the voltage controller what v ccp voltage should be applied to the cpu. the v ccp voltage applied to the processor changes as the power requirements of the processor change. the vid is compared with v ccp1 only. note that when the vids are enabled, the lsb value for v ccp1 becomes 0.0125 v (see table 16 ) . the vid values can represent voltages from 0.8375 v to 1.6 v. the vid code is sampled by the adt7462 every 11 s and is stored in register 0x97. once the vid code has been stable (that is, does not change) for 55 s, the measured v ccp is then compared with the vid code. the comparison table used is for either the vr10 or the vr11 specification (set by bit 6 of register 0x00). if the vid code and the measured v ccp do not match within a certain limit, an alert is generated. the vid value decoded and the v ccp measurement must be within a window controlled by the vid high and low limits. the vid is compared with v ccp1 only. register 0x78 holds the 4-bit vid high and low limits. the high limit has a range of 0 mv to 375 mv with a resolution of 25 mv (four bits). the low limit has a range of 0 mv to ?187.5 mv with a resolution of 12.5 mv (four bits). the high limit is used in a greater-than comparison, and the low limit is used in a less-than-or-equal-to comparison. note that if both limits are set to 0x00, because the low limit is less than or equal to the comparison, an alert always results. therefore, the minimum value for low limit is 0x01. if the v ccp voltage measured and the vid code do not match to within the programmed limit, status bit 6 of the digital status register is set (register 0xbe). this, in turn, can generate an alert if it is not masked.
adt7462 rev. a | page 30 of 92 example vid high limit: 100 mv (register 0x78), four msbs set to 0100. vid low limit: 50 mv (register 0x78), four lsbs set to 0100. vid value equates to 1.1 v. this is the read vid decoded, using either vr10 or vr11 tables. v ccp1 must be in the window of 1.05 v to 1.2 v. if the v ccp1 value is outside this window, the status bit is set and an alert is generated. to cle ar an alert generated in this way, read the digital status register. if the vid code and v ccp are now matching within the programmed window (that is, the error condition that caused the alert has gone away), then the status bit is reset and so is the alert . the vid to v ccp voltage tables for both vr10 and vr11 can be found on the intel website. see the voltage regulator module ( vrm) and enterprise voltage regulator-down (evrd) 10.0 design guidelines , page 18 and page 19, for additional information.
adt7462 rev. a | page 31 of 92 status and mask registers and alert status registers each measured temperature and voltage has an associated high and low limit. the measured values are compared with these programmable limits. the results of these comparisons are stored in the status registers. a logic 0 in the status register represents an in-limit comparison, while a logic 1 represents an out-of-limit comparison. once a status bit is set, it remains set until the status register is read by the smbus master. once read, the status bit is cleared if the error condition has gone away. the status registers are duplicated to accommodate situations where there are two smbus masters. if one master reads the host status registers and conse- quently clears them, the second master has no way of knowing what bits were set and what bits were cleared. the second smbus master can read from the duplicate bmc status registers to determine which status bits were set. table 23 is a list of the status registers and corresponding addresses. table 23. status registers register name host address bmc address thermal status register 1 0xb8 0xc0 thermal status register 2 0xb9 0xc1 thermal status register 3 0xba voltage status register 1 0xbb 0xc3 voltage status register 2 0xbc 0xc4 fan status register 1 0xbd 0xc5 digital status register 1 0xbe 0xc6 gpio status register 0xbf alert output the adt7462 has an smbus alert output that is asserted when one of the status bits is set. this is to alert the master that an out-of-limit measurement has taken place or that there is a fault on one of the fan channels. an alert is generated as a result of a status bit being set in any of the registers. high limit temperature sticky status bit temp back in limit (statusbitstaysset) cleared on read (temp below limit) smbalert 05569-029 figure 39. alert and status bit behavior figure 39 shows how the alert output and sticky status bits behave. when a limit is exceeded, the corresponding status bit is set to 1. the status bit remains set until the error condition goes away and the status register is read. the status bits are referred to as sticky because they remain set until read by software. this ensures that an out-of-limit event cannot be missed, if software is polling the device periodically. note that the alert output remains low for the entire duration that a reading is out of limit and until the status register has been read. mask registers the user has the option of masking any of the individual status bits that generate an alert . this is achieved by setting the appropriate bit in the mask registers. the alert output is not asserted on the setting of a status bit if it has been masked. the status bit itself is not affected and continues to be set when an out-of-limit condition exists. table 24 is a list of the mask registers and corresponding addresses. table 24. mask registers register name register address thermal mask register 1 0x30 thermal mask register 2 0x31 voltage mask register 1 0x32 voltage mask register 2 0x33 fan mask register 0x34 digital mask register 0x35 gpio mask register 0x36
adt7462 rev. a | page 32 of 92 fan control fan drive using pwm control the adt7462 uses pulse-width modulation (pwm) to control fan speed. control relies on varying the duty cycle (or on/off ratio) of a square wave applied to the fan to vary the fan speed. the advantage of using pwm control is that it uses a very simple external circuit. the specific circuit used depends upon the type of fan. there are three main fan types in use: 2-wire fans, 3-wire fans, and 4-wire fans. the 2-wire fan has only power and ground connections. the 3-wire fan has power and ground connections and a tach output to indicate the speed of the fan. the 4-wire fan has power and ground connections, a tach output, and a pwm input. the pwm input is connected directly to the pwm drive of the adt7462 and is used to control the speed of the fans. for 2-wire and 3-wire fans, the low frequency pwm drive signal should be selected. for 4-wire fans, the high frequency pwm drive signal should be selected. using the adt7462 with 2-wire fans figure 40 shows the most typical circuit used with a 2-wire fan and illustrates how a 2-wire fan can be connected to the adt7462. the low frequency pw m mode must be selected when using a 2-wire fan. adt7462 pwm tach 5v or 12v fan q1 ndt3055l 3.3v + v 10k ? typical 1n4148 0.01f r sense 2 ? typical 0 5569-030 figure 40. driving a 2-wire fan using the adt7462 with 3-wire fans figure 41 shows the most typical circuit used with a 3-wire fan. adt7462 tach/ain pwm 12v fan q1 ndt3055l 3.3v 12 v 12 v 10k ? 4.7k ? 10k ? 10k ? 1n4148 05569-031 figure 41. driving a 3-wire fan the external circuitry required is very simple. a mosfet, such as the ndt3055l, is used as the pass device. the specifications of the mosfet depend on the maximum current required by the fan being driven. a typical pc fan can draw a nominal cur- rent ranging from a few hundred milliamps to over an amp of current. depending on the current rating of the fan, a sot device can be used where board space is a concern. if several fans in parallel are driven from a single pwm output or if larger server fans are driven, the mosfet must handle the higher current requirements. the only other stipulation is that the mosfet should have a gate voltage drive, v gs < 3.3 v, for direct interfacing to the pwm pins. v gs can be greater than 3.3 v as long as the pull-up on the gate is tied to 5 v. the mosfet should also have a low on resistance to ensure that there is not a significant voltage drop across the fet, which would reduce the voltage applied across the fan and reduce the full speed of the fan. figure 41 uses a 10 k pull-up resistor for the tach signal. this assumes that the tach signal is an open-collector from the fan. in all cases, the tach signal from the fan must be kept below 5 v maximum to prevent damaging the adt7462. if in doubt as to whether the fan used has an open-collector or totem-pole tach output, use one of the input signal condition- ing circuits shown in the fan speed measurement section. driving a 3-wire fan with a pwm signal makes the fan speed measurement more difficult because the tach signal is chopped by the pwm drive signal. pulse stretching is required in this case to make accurate fan speed measurements. for more information, see the fan speed measurement section.
adt7462 rev. a | page 33 of 92 using the adt7462 with 4-wire fans figure 42 shows the most typical circuit used with 4-wire fans. adt7462 tach pwm 12v, 4-wire fan 3.3v or 5v 12 v 12 v 2k ? 4.7k ? 10k ? 10k ? v cc tach tach pwm 0 5569-032 figure 42. driving a 4-wire fan because the electronics in a 4-wire fan are powered continuously, unlike previous pwm driven/powered fans, 4-wire fans tend to perform better than 3-wire fans, especially for high frequency applications. 4-wire frames also eliminate the requirement for pulse stretching, because the tach signal is always available. driving two fans from each pwm note that the adt7462 has up to eight tach inputs available for fan speed measurement, but only four pwm drive outputs. if all eight fans are being used in the system, two fans should be driven in parallel from each pwm output. figure 43 shows how to drive two fans in parallel using the ndt3055l mosfet. this information is relevant for low frequency mode only (2-wire and 3-wire fans), because the pwm and tachs need to be synchronized to obtain accurate fan speed measurements using pulse stretching (see the fan speed measurement with pulse stretching section). in high frequency mode and when using 4-wire fans, the tach signal is always valid because the fan is always powered on. note that because the mosfet can handle up to 3.5 a, it is simply a matter of connecting another fan directly in parallel with the first. care should be taken in designing drive circuits with transistors and fets to ensure that the pwm pins are not required to source current and that they sink less than the 8 ma maximum current specified on the mosfet data sheet. adt7462 pwm3 tach3 tach7 3.3v 3.3v 3.3 v +v +v tach tach q1 ndt3055l 1n4148 5v or 12v fan 5v or 12v fan 10k ? typical 10k ? typical 10k ? typical 05569-033 figure 43. interfacing two fans in parallel to a pwm output using a single n-channel mosfet
adt7462 rev. a | page 34 of 92 fan speed measurement and control tach inputs pin 1, pin 2, pin 3, pin 4, pin 7, pin 8, pin 21, and pin 22 are tach inputs intended for fan speed measurement. signal conditioning in the adt7462 accommodates the slow rise and fall times typical of fan tachometer outputs. the maxi- mum input signal range is 0 v to 5 v, even when v cc is less than 5 v. in the event that these inputs are supplied from fan outputs that exceed 0 v to 5 v, either resistive attenuation of the fan signal or diode clamping must be included to keep inputs within an acceptable range. figure 44 to figure 47 show circuits for most common fan tach circuits. if the fan tach output has a resistive pull-up to v cc , it can be connected directly to the fan input, as shown in figure 44. 12v v cc pull-up 4.7k ? typical tach output fan speed counter tach adt7462 05569-034 figure 44. fan with tach pull-up to v cc if the fan output has a resistive pull-up to 12 v (or other voltage greater than 5 v), the fan output can be clamped with a zener diode, as shown in figure 45. the zener diode voltage should be chosen so that it is greater than v ih of the tach input but less than 5 v, allowing for the voltage tolerance of the zener diode. a value of between 3 v and 5 v is suitable. 12v v cc pull-up 4.7k ? typical tach output fan speed counter tach adt7462 zd1* *choose zd1 voltage approximately 0.8 v cc. 0 5569-035 figure 45. fan with tach pull-up to voltage > 5 v (example, 12 v), clamped with zener diode if the fan has a strong pull-up (less than 1 k) to 12 v or a totem-pole output, a series resistor can be added to limit the zener current, as shown in figure 46. alternatively, a resistive attenuator can be used, as shown in figure 47. r1 and r2 should be chosen such that 2 v < v pull-up r2 /( r pull-up + r1 + r2 ) < 5 v the fan inputs have an input resistance of nominally 160 k to ground, so this should be taken into account when calculating resistor values. with a pull-up voltage of 12 v and a pull-up resistor of less than 1 k, suitable values for r1 and r2 would be 100 k and 47 k. this gives a high input voltage of 3.83 v. 5v or 12v v cc pull-up typ <1k ? or totem pole tach output fan speed counter tach adt7462 zd1 zener* fan *choose zd1 voltage approximately 0.8 v cc. r1 10k ? 0 5569-036 figure 46. fan with strong tach pull-up to > v cc or totem-pole output, clamped with a zener diode and resistor 12v v cc <1k ? tach output fan speed counter tach adt7462 r2* *see text r1* 0 5569-037 figure 47. fan with strong tach pull-up to > v cc or totem-pole output, attenuated with r1/r2 fan speed measurement the method of fan speed measurement when using 3-wire fans differs from that used with 4-wire fans. when 3-wire fans are in use, power is continuously applied and removed from the fan, thereby chopping the tach information. as a result, every time a fan speed measurement is to be made, the fan must be switched on for a long enough period of time that a measurement can be made. this is called pulse stretching. with 4-wire fans, power is always applied to the fan, so fan speed measurements can be made continuously, and there is no need for pulse stretching. pulse stretching is also not necessary when driving a 3-wire fan with a dc input. the fan speed measurement without pulse stretching section and the fan speed measurement with pulse stretching section describe how fan speed is measured both when pulse stretching is required and when it is not. fan speed measurement without pulse stretching fan speed is measured by the adt7462, and the result is stored in the fan tach value registers. the fan counter does not count the fan tach output pulses directly because the fan speed can be less than 1000 rpm, and it would take several seconds to accumulate a reasonably large and accurate count. instead, the period of the fan revolution is measured by gating an on-chip 90 khz oscillator into the input of a 16-bit counter for n periods of the fan tach output (see figure 48), so the accumulated count is actually proportional to the fan tachometer period and inversely proportional to the fan speed.
adt7462 rev. a | page 35 of 92 1 2 3 4 clock pwm tach 05569-038 figure 48. fan speed measurement to enable continuous measurement for 3-wire fans, set the corresponding dc bit for the tach input in the tach configu- ration register. this bit is set automatically when the hf pwm is in use with 4-wire fans. fan speed measurement with pulse stretching the method for measuring fan speed for 3-wire fans requiring pulse stretching is similar to the method described in the fan speed measurement without pulse stretching section for continuous measurements. the main difference is that the pwm drive must be synchronized to the tach input so that the adt7462 knows that pulse stretching is taking place while the tach is being measured. pwm1 is synchronized with tach1 and tach2. pwm2 is synchronized with tach3 and tach4. pwm3 is synchronized with tach5 and tach6. pwm4 is synchronized with tach7 and tach8. driving and measuring the speed of two fans from one pwm output when pulse stretching is enabled, the adt7462 measures fan speed once a second. the counter then counts up from the first to the third tach pulse; this value is stored in the tach value register. the pwm drive returns to its previous programmed value. each tach input is synchronized to a particular pwm output. the pwm and tach pins must be connected as shown in figure 49 to ensure that pulse stretching is synchronized between the pwm output and the tach inputs, and an accurate fan speed measurement is made on each fan. pwm1 pwm2 pwm3 pwm4 fan 1 fan 2 fan 3 fan 4 tach1 tach2 tach3 tach4 fan 5 fan 6 fan 7 fan 8 tach5 tach6 tach7 tach8 05569-087 figure 49. synchronizing fan pwm output and tach inputs driving and measuring the speed of one fan from one pwm output if four single fans are being controlled and measured by the adt7462, the following configuration should be used. this applies only to 3-wire fans controlled using low frequency pwm with pulse stretching enabled. fan 1 is driven by pwm1 and measured using tach1. fan 2 is driven by pwm2 and measured using tach3. fan 3 is driven by pwm3 and measured using tach5. fan 4 is driven by pwm4 and measured using tach7. pwm1 pwm2 pwm3 pwm4 fan 1 fan 2 tach1 tach3 fan 3 fan 4 tach5 tach7 05569-088 figure 50. driving and measuring the speed on a single fan the pwm output is pulse stretched until a valid tach is read on both tach inputs synchronized to the particular pwm output. if one fan is connected to one pwm output, the pwm output is pulse stretched until the counter has timed out on the disconnected tach input. in this case, the pulse is stretching longer than necessary in an effort to sense a disconnected fan. the speed of the connected fan may be increased and an audible change in fan speed may be observed. there are two options to prevent the pwm output from being stretched longer than necessary in this case. ? connect the two synchronized tach inputs together; for example, if pwm1 is driving a single fan being sensed on tach1 only, connect tach1 and tach2 together. ? turn off pulse stretching on the unused tach input; that is, if pwm1 is driving a single fan being sensed on tach1 only, turn off pulse stretching on tach 2 in register 0x08. in this register, bit 0 controls pulse stretching on tach1 and tach5. bit 1 controls pulse stretching on tach2 and tach6. bit 2 controls pulse stretching on tach3 and tach7. bit 3 controls pulse stretching on tach4 and tach8. note that the tach assignments in this register differ from the tachs synchronized to each pwm output. therefore, if the intention is to drive and sense four fans, connecting the tachs together as described in option 1 allows pulse stretching on all channels.
adt7462 rev. a | page 36 of 92 to enable fan speed measurements four times a second, set the fast bit (bit 0) of configuration register 2 (0x02). when the fast bit is set, fan tach readings are updated every 250 ms. fan speed measurement registers fan speed measurement involves a 2-register read for each measurement. the low byte should be read first. this causes the high byte to be frozen until both high and low byte registers have been read, preventing erroneous tach readings. the fan tachometer reading registers report back the number of 11.11 s period clocks (90 khz oscillator) gated to the fan speed counter, from the rising edge of the first fan tach pulse to the rising edge of the third fan tach pulse (because two pulses per revolution are being counted). because the device is essentially measuring the fan tach period, the higher the count value, the slower the fan is actually running. a 16-bit fan tachometer reading of 0xffff indicates either that the fan has stalled or is running very slowly (<100 rpm). the actual fan tach period is being measured; therefore, an alert is generated if the reading falls below a fan tach limit. this alert sets the appropriate status bit and can be used to generate an smbalert . the tach limit is an 8-bit value that is compared with the tach high byte of the tach reading. table 25. tachometer value and limit registers tach low byte value register high byte value register 8-bit limit register tach1 0x98 0x99 0x78 tach2 0x9a 0x9b 0x79 tach3 0x9c 0x9d 0x7a tach4 0x9e 0x9f 0x7b tach5 0xa2 0xa3 0x7c tach6 0xa4 0xa5 0x7d tach7 0xa6 0xa7 0x7e tach8 0xa8 0xa9 0x7f calculating fan speed assuming a fan with two pulses per revolution (and two pulses per revolution being measured), fan speed is calculated by fan speed (rpm) = ( freq 60)/ fan tachometer reading (1) where: fan tachometer reading is the 16-bit fan tachometer reading. freq is the oscillator frequency, 90 khz. example tach1 high byte (register 0x99) = 0x17 tach1 low byte (register 0x98) = 0xff what is the speed of fan 1 in rpm? fan 1 tachometer reading = 0x17ff = 6143 decimal (2) rpm = ( freq 60)/ fan 1 tachometer reading (3) rpm = (90000 60)/6143 (4) fan speed = 879 rpm (5) if the fan is a 6-pole fan, the count value is representative of 2/3 of a revolution. therefore, the result of equation 5 should be divided by 1.5. similarly, if the fan used is an 8-pole fan, then the result should be divided by 2. fan spin-up the adt7462 has a unique fan spin-up function. it spins the fan at 100% pwm duty cycle until two tach pulses are detected on the tach input. once two tach pulses have been detected, the pwm duty cycle goes to the expected running value, for example, 33%. the advantage of this process is that fans have different spin-up characteristics and require different times to overcome inertia. the adt7462 runs the fans just fast enough to overcome inertia and the fans are quieter on spin-up than fans programmed to spin up for a given spin-up time. fan start-up timeout to prevent false interrupts being generated as a fan spins up (because it is below running speed), the adt7462 includes a fan start-up timeout function. during this time, the adt7462 looks for two tach pulses. if two tach pulses are not detected, an interrupt is generated. using configuration register 1 (0x01), bit 4, this functionality can be changed to spinning the fans for a programmable time instead of two tach pulses. the start-up timeout for each pwm drive is programmed by bits [2:0] in the pwmx configuration registers. pwm1 configuration register = register 0x21 pwm2 configuration register = register 0x22 pwm3 configuration register = register 0x23 pwm4 configuration register = register 0x24 table 26. fan start-up timeout bit code start-up timeout 000 no start-up timeout 001 100 ms 010 250 ms 011 400 ms 100 667 ms 101 1 sec 110 2 sec 111 32 sec
adt7462 rev. a | page 37 of 92 pwm logic state the pwm outputs can be programmed high for 100% duty cycle (noninverted) or low for 100% duty cycle (inverted). this is programmed for each pwm drive in the pwmx configuration registers using the inv bit (bit 4). 0 = active high pwm outputs. 1 = active low pwm outputs. low frequency mode pwm drive frequency the pwm drive frequency can be adjusted for the application. the adt7462 supports both high frequency and low frequency pwm. high or low frequency pwm mode is selected in register 0x02, bit 2. in high frequency mode, the pwm drive frequency is always 22.5 khz and cannot be changed. register 0x25 and register 0x26 configure the pwm frequency in low fre- quency mode for pwm1 to pwm4. pwm drive frequency 1 is set using bits [4:2] of the pwm1 and pwm2 frequency register (0x25). pwm drive frequency 2 is set using bits [7:5] of the pwm1 and pwm2 frequency register (0x25). pwm drive frequency 3 is set using bits [4:2] of the pwm3 and pwm4 frequency register (0x26). pwm drive frequency 4 is set using bits [7:5] of the pwm3 and pwm4 frequency register (0x26). table 27. low frequency pwm options bit code frequency 000 11 hz 001 14.7 hz 010 22.1 hz 011 29.4 hz 100 35.3 hz 101 44.1 hz 110 58.8 hz 111 88.2 hz fan speed control the adt7462 controls fan speed using two different modes: automatic and manual. in automatic fan speed control mode, fan speed is automatically varied with temperature and without cpu intervention, after initial parameters are set up. the advantage of this mode is that if the system hangs, the system is protected from overheating. the automatic fan speed control incorporates a feature called dynamic t min calibration. this feature reduces the design effort required to program the automatic fan speed control loop. for more information on how to program the automatic fan speed control loop and dynamic t min operation, see the programming the automatic fan speed control loop section. in manual fan speed control mode, the adt7462 allows the duty cycle of any pwm output to be manually adjusted. this is useful if the user wants to change fan speed in the software or adjust pwm duty cycle output for test purposes. bits [7:5] of register 0x21 to register 0x24 (pwm configuration registers) control the behavior of each pwm output. under manual con- trol, each pwm output can be manually updated by writing to register 0xaa to register 0xad (pwm duty cycle registers). programming the pwm current duty cycle registers the pwm current duty cycle registers are 8-bit registers that allow the pwm duty cycle for each output to be set anywhere from 0% to 100% in steps of 0.39%. the value to be programmed into the pwm min register is given by value (decimal) = pwm min /0.39 example 1 for a pwm duty cycle of 50%, value (decimal) = 50/0.39 = 128 decimal value = 128 decimal or 0x80 example 2 for a pwm duty cycle of 33%, value (decimal) = 33/0.39 = 85 decimal value = 84 decimal or 0x54 pwm duty cycle registers register 0xaa pwm1 duty cycle = 0x00 (0% default) register 0xab pwm2 duty cycle = 0x00 (0% default) register 0xac pwm3 duty cycle = 0x00 (0% default) register 0xad pwm4 duty cycle = 0x00 (0% default) by reading the pwmx current duty cycle registers, the user can keep track of the current duty cycle on each pwm output, even when the fans are running in automatic fan speed control mode or acoustic enhancement mode. vary pwm duty cycle with 8-bit resolution 05569-039 figure 51. control pwm duty cycle manually with a resolution of 0.39%
adt7462 rev. a | page 38 of 92 programming the automatic fan speed control loop note that to better understand the automatic fan speed control loop, use of the adt7462 evaluation board and software is strongly recommended while reading this section. this section provides the system designer with an understanding of the automatic fan control loop and provides step-by-step guidance on effectively evaluating and selecting critical system parameters. to optimize system characteristics, the designer needs to carefully plan system configuration, including the number of fans, where they are located, and what temperatures are being measured in the particular system. the mechanical or thermal engineer who is tasked with the system thermal characterization should also be involved at the beginning of the process. automatic fan control overview the adt7462 can automatically control the speed of fans based upon the measured temperature. this is done independently from cpu intervention once initial parameters are set up. the adt7462 has a local temperature sensor and up to three remote temperature channels that can be connected to a cpu on-chip thermal diode (available on intel pentium class and other cpus/gpus). these four temperature channels can be used as the basis for automatic fan speed control to drive fans using pulse-width modulation (pwm). automatic fan speed control reduces acoustic noise by optimizing fan speed according to accurately measured temperature. reducing fan speed can also decrease system current consumption. the automatic fan speed control mode is very flexible, owing to the number of programmable parameters, including t min and t range . the t min and t range values for a temperature channel and, therefore, for a given fan, are critical because they define the thermal characteristics of the system. the thermal validation of the system is one of the most important steps in the design process, so these values should be selected carefully. figure 52 gives a top-level overview of the automatic fan control circuitry on the adt7462. from a systems-level perspective, up to four system temperatures can be monitored and used to control four pwm outputs. the four pwm outputs can be used to control up to eight fans. the adt7462 allows the speed of eight fans to be monitored. the remote 1 and remote 2 temperature channels have a thermal calibration block, allowing the designer to individually configure the thermal characteristics of those temperature channels. for example, the cpu fan can be run when cpu temperature increases above 60c and a chassis fan can be run when the local temperature increases above 45c. at this stage, the designer has not assigned these thermal calibration settings to a particular fan drive (pwm) channel. the right side of figure 52 shows controls that are fan-specific. the designer has control over individual parameters such as minimum pwm duty cycle, fan speed failure thresholds, and even ramp control of the pwm outputs. automatic fan control, then, ultimately allows graceful fan speed changes that are less perceptible to the system user. mux thermal calibration 0% t min t range thermal calibration 100% 0% t min t range thermal calibration 100% 0% t min t range remote 1 temp local temp remote 2 temp tachometer 1 measurement pwm config pwm min pwm1 ramp control (acoustic enhancement) pwm generator tachometer 2 measurement pwm config pwm min pwm2 ramp control (acoustic enhancement) pwm generator tachometer 3 and 4 measurement pwm config pwm min pwm3 ramp control (acoustic enhancement) pwm generator 100% tach1 tach2 tach3 05569-040 figure 52. automatic fan control block diagram
adt7462 rev. a | page 39 of 92 step 1configuring the mux first, the user needs to decide how many temperature channels are being measured and how many fans need to be controlled and monitored. when these decisions have been made, the fans can be assigned to particular temperature channels. not only can fans be assigned to individual channels, but the behavior of the fans is also configurable. for example, fans can be run under automatic fan control; they can be run manually (under software control); or they can be run at the fastest speed calculated by multiple temperature channels. the mux is the bridge between temperature measurement channels and the three pwm outputs. bits [7:5] (bhvr) of register 0x21, register 0x22, register 0x23, and register 0x24 (pwm configuration registers) control the behavior of the fans connected to the pwm1, pwm2, pwm3, and pwm4 outputs. the values selected for these bits determine how the mux connects a temperature measurement channel to a pwm output (see figure 53). automatic fan control mux options bits [7:5] (bhvr), of register 0x21, register 0x22, register 0x23, and register 0x24, control the behavior of the corresponding pwm outputs (see table 61 and table 62). the fastest speed calculated options pertain to controlling one pwm output based on multiple temperature channels. the thermal characteristics of the three temperature zones can be set to drive a single fan. an example is the fan turning on when the remote 1 temperature exceeds 60c or when the local temperature exceeds 45c. step 2t min settings for thermal calibration channels t min is the temperature at which the fans start to turn on under automatic fan control. the speed at which the fan runs at t min is programmed later. the t min values chosen are temperature channel-specific; for example, 25c for ambient channel, 30c for vrm temperature, and 40c for processor temperature. t min is an 8-bit value, either twos complement or offset 64, that can be programmed in 1c increments. there is a t min register associated with each temperature measurement channel: local, remote 1, remote 2, and remote 3. when the t min value is exceeded, the fan turns on and runs at the minimum pwm duty cycle. the fan turns off after the temperature has dropped below t min ? t hyst . mux rear chassis front chassis cpu fan sink remote 1 = ambient temp local = vrm temp remote 2 = cpu temp pwm1 pwm2 tach1 tach2 tach3 pwm3 mux thermal calibration 0% t min t range thermal calibration 100% 0% t min t range thermal calibration 100% 0% t min t range tachometer 1 measurement pwm config pwm min ramp control (acoustic enhancement) pwm generator tachometer 2 measurement pwm config pwm min ramp control (acoustic enhancement) pwm generator tachometer 3 and 4 measurement pwm config pwm min ramp control (acoustic enhancement) pwm generator 100% 05569-041 figure 53. assigning temperatur e channels to fan channels
adt7462 rev. a | page 40 of 92 to overcome fan inertia, the fan is spun up until two valid tach rising edges are counted. see the fan spin-up section for more details. in some cases, primarily for psycho-acoustic reasons, the fan should never switch off below t min . the corresponding bits in register 0x25 and register 0x26 should be set to keep the fans running at the pwm minimum duty cycle, if the temperature falls below t min . t min registers register 0x5c, local temperature t min = 0x9a (90c) register 0x5d, remote 1 temperature t min = 0x9a (90c) register 0x5e, remote 2 temperature t min = 0x9a (90c) register 0x5f, remote 3 temperature t min = 0x9a (90c) pwm1 and pwm2 frequency register (0x25) bit 0 (min 1) = 0. pwm1 is off (0% pwm duty cycle) when temperature is below t min ? t hyst . bit 0 (min 1) = 1. pwm1 runs at pwm1 minimum duty cycle below t min ? t hyst . bit 1 (min 2) = 0. pwm2 is off (0% pwm duty cycle) when temperature is below t min ? t hyst . bit 1 (min 2) = 1. pwm2 runs at pwm2 minimum duty cycle below t min ? t hyst . pwm3 and pwm4 frequency register (0x26) bit 0 (min 3) = 0. pwm3 is off (0% pwm duty cycle) when temperature is below t min ? t hyst . bit 0 (min 3) = 1. pwm3 runs at pwm3 minimum duty cycle below t min ? t hyst . bit 1 (min 4) = 0. pwm4 is off (0% pwm duty cycle) when temperature is below t min ? t hyst . bit 1 (min 4) = 1. pwm4 runs at pwm4 minimum duty cycle below t min ? t hyst . rear chassis front chassis cpu fan sink local = vrm temp pwm1 pwm2 tach1 tach2 tach3 pwm3 remote 1 = ambient temp remote 2 = cpu temp mux thermal calibration 0% t min t range thermal calibration 100% 0% t min t range thermal calibration 100% 0% t min t range tachometer 1 measurement pwm config pwm min ramp control (acoustic enhancement) pwm generator tachometer 2 measurement pwm config pwm min ramp control (acoustic enhancement) pwm generator tachometer 3 and 4 measurement pwm config pwm min ramp control (acoustic enhancement) pwm generator 100% 0% 100% p w m d u t y c y c l e t min 05569-042 figure 54. understanding the t min parameter
adt7462 rev. a | page 41 of 92 step 3pwm min for each pwm (fan) output pwm min is the minimum pwm duty cycle at which each fan in the system runs. it is also the start speed for each fan under automatic fan control when the temperature rises above t min . for maximum system acoustic benefit, pwm min should be as low as possible. depending on the fan used, the pwm min setting is usually in the 20% to 33% duty cycle range. this value can be found through fan validation. temperature t min 100% pwm min 0% pwm duty cycle 05569-043 figure 55. pwm min determines minimum pwm duty cycle at t min more than one pwm output can be controlled from a single temperature measurement channel. for example, remote 1 temperature can control pwm1 and pwm2 outputs. if two different fans are used on pwm1 and pwm2, the fan characteris- tics can be set up differently. as a result, fan 1, driven by pwm1, can have a different pwm min value than that of fan 2 connected to pwm2. figure 56 illustrates this as pwm1 min (the front fan) turns on at a minimum duty cycle of 20%, while pwm2 min (the rear fan) turns on at a minimum duty cycle of 40%. note, however, that both fans turn on at exactly the same temperature, defined by t min . temperature t min 100% pwm1 min 0% pwm duty cycle p w m 1 p w m 2 pwm2 min 05569-044 figure 56. operating two different fans from a single temperature channel programming the pwm min registers the pwm min registers are 8-bit registers that allow the minimum pwm duty cycle for each output to be configured anywhere from 0% to 100%. this allows the minimum pwm duty cycle to be set in steps of 0.39%. the value to be programmed into the pwm min register is given by value (decimal) = pwm min /0.39 example 1 for a minimum pwm duty cycle of 50%, value (decimal) = 50/0.39 = 128 (decimal) value = 128 (decimal) or 0x80 (hexadecimal) example 2 for a minimum pwm duty cycle of 33%, value (decimal) = 33/0.39 = 85 (decimal) value = 85 (decimal) or 0x54 (hexadecimal) pwm min registers register 0x28, minimum pwm1 duty cycle = 0x80 (50% default) register 0x29, minimum pwm2 duty cycle = 0x80 (50% default) register 0x2a, minimum pwm3 duty cycle = 0x80 (50% default) register 0x2b, minimum pwm4 duty cycle = 0x80 (50% default) note on fan speed and pwm duty cycle the pwm duty cycle does not directly correlate to fan speed in rpm. running a fan at 33% pwm duty cycle does not equate to running the fan at 33% speed. driving a fan at 33% pwm duty cycle actually runs the fan at closer to 50% of its full speed. this is because fan speed in % rpm generally relates to the square root of pwm duty cycle. given a pwm square wave as the drive signal, fan speed in rpm approximates to 10 % = cycle duty pwm fanspeed step 4pwm max for pwm (fan) outputs pwm max is the maximum duty cycle that each fan in the system runs at under the automatic fan speed control loop. for maximum system acoustic benefit, pwm max should be as low as possible but should be capable of maintaining the processor temperature limit at an acceptable level. if the therm temperature limit is exceeded, the fans are still boosted to 100% for fail-safe cooling. there is one pwm max limit (register 0x2c) for all fan channels. temperature t min 100% pwm min 0% pwm duty cycle pwm max 05569-045 figure 57. pwm max determines maximum pwm duty cycle below the therm temperature limit
adt7462 rev. a | page 42 of 92 programming the pwm max register the pwm max register (0x2c) is an 8-bit register that allows the maximum pwm duty cycle for the outputs to be configured anywhere from 0% to 100%. this allows the maximum pwm duty cycle to be set in steps of 0.39%. the value to be programmed into the pwm max register is given by value (decimal) = pwm max /0.39 example 1 for a maximum pwm duty cycle of 50%, value (decimal) = 50/0.39 = 128 (decimal) value = 128 (decimal) or 0x80 (hexadecimal) example 2 for a maximum pwm duty cycle of 75%, value (decimal) = 75/0.39 = 192 (decimal) value = 192 (decimal) or 0xc0 (hexadecimal) pwm max register register 0x2c, maximum pwm1 to pwm4 duty cycle = 0xc0 (75% default) see the note on fan speed and pwm duty cycle section for more information. step 5t range for temperature channels t range is the range of temperatures over which automatic fan control occurs when the programmed t min temperature is exceeded. t range is a temperature slope, not an arbitrary value; that is, a t range of 40c holds true only for pwm min = 33%. if pwm min is increased or decreased, the effective t range changes. temperature t min 100% pwm min 0% pwm duty cycle t range 05569-046 figure 58. t range parameter affects cooling range the t range or fan control slope is determined by the following procedure: 1. determine the maximum operating temperature for that channel (for example, 70c). 2. determine experimentally the fan speed (pwm duty cycle value) that does not exceed the temperature at the worst- case operating points. (for example, 70c is reached when the fans are running at 50% pwm duty cycle.) 3. determine the slope of the required control loop to meet these requirements. 4. using the adt7462 evaluation software, this functionality can be graphically programmed and visualized. ask your local analog devices, inc. representative for details. t min 100% 33% 0% pwm duty cycle 50% 30c 40c 05569-047 figure 59. adjusting pwm min affects t range t range is implemented as a slope, which means that as pwm min is changed, t range changes, but the actual slope remains the same. the higher the pwm min value, the smaller the effective t range ; that is, the fan reaches full speed (100%) at a lower temperature. 05569-048 t min 100% 33% 0% pwm duty cycle 50% 30c 40c 25% 10% 45c 54c figure 60. increasing pwm min changes effective t range
adt7462 rev. a | page 43 of 92 for a given t range value, the temperature at which the fan runs at full speed for different pwm min values can be easily calculated by t max = t min + ( max dc ? min dc ) t range /170 where: t max is the temperature at which the fan runs full speed. t min is the temperature at which the fan turns on. max dc is the maximum duty cycle (100%) = 255 decimal. min dc is equal to pwm min . t range is the pwm duty cycle vs. temperature slope. example 1 calculate t max , given that t min = 30c, t range = 40c, and pwm min = 10% duty cycle = 26 (decimal). t max = t min + ( max dc ? min dc ) t range /170 t max = 30c + (100% ? 10%) 40c/170 t max = 30c + (255 ? 26) 40c/170 t max = 84c ( effective t range = 54c) example 2 calculate t max , given that t min = 30c, t range = 40c, and pwm min = 25% duty cycle = 64 (decimal). t max = t min + ( max dc ? min dc ) t range /170 t max = 30c + (100% ? 25%) 40c/170 t max = 30c + (255 ? 64) 40c/170 t max = 75c ( effective t range = 45c) example 3 calculate t max , given that t min = 30c, t range = 40c, and pwm min = 33% duty cycle = 85 (decimal). t max = t min + ( max dc ? min dc ) t range /170 t max = 30c + (100% ? 33%) 40c/170 t max = 30c + (255 ? 85) 40c/170 t max = 70c ( effective t range = 40c) example 4 calculate t max , given that t min = 30c, t range = 40c, and pwm min = 50% duty cycle = 128 (decimal). t max = t min + ( max dc ? min dc ) t range /170 t max = 30c + (100% ? 50%) 40c/170 t max = 30c + (255 ? 128) 40c/170 t max = 60c ( effective t range = 30c) selecting a t range slope the t range value can be selected for each temperature channel: local, remote 1, remote 2, and remote 3. bits [7:4] (range) of register 0x60 to register 0x63 define the t range value for each temperature channel (see table 85 and table 86 ) . summary of t range function when using the automatic fan control function, the temperature at which the fan reaches full speed can be calculated by t max = t min + t range (6) equation 6 holds true only when pwm min is equal to 33% pwm duty cycle. increasing or decreasing pwm min changes the effective t range , although the fan control still follows the same pwm duty cycle to temperature slope. the effective t range for different pwm min values can be calculated using equation 7. t max = t min + ( max dc ? min dc ) t range /170 (7) where ( max dc ? min dc ) t range /170 is the effective t range value. figure 61 shows pwm duty cycle vs. temperature for each t range setting. the lower graph shows how each t range setting affects fan speed vs. temperature. as shown in the graph, the effect on fan speed is nonlinear.
adt7462 rev. a | page 44 of 92 temperature above t min 0 20406080100120 0 fan speed (% of max) 10 20 30 40 50 60 70 80 90 100 temperature above t min 0 20406080100120 0 pwm duty cycle (%) 10 20 30 40 50 60 70 80 90 100 2c 80c 53.3c 40c 32c 26.6c 20c 16c 13.3c 10c 8c 6.67c 5c 4c 3.33c 2.5c 2c 80c 53.3c 40c 32c 26.6c 20c 16c 13.3c 10c 8c 6.67c 5c 4c 3.33c 2.5c 0 5569-049 figure 61. t range vs. actual fan speed profile temperature above t min 0 20406080100120 0 pwm duty cycle (%) 10 20 30 40 50 60 70 80 90 100 temperature above t min 0 20406080100120 0 fan speed (% of max) 10 20 30 40 50 60 70 80 90 100 2c 80c 53.3c 40c 32c 26.6c 20c 16c 13.3c 10c 8c 6.67c 5c 4c 3.33c 2.5c 2c 80c 53.3c 40c 32c 26.6c 20c 16c 13.3c 10c 8c 6.67c 5c 4c 3.33c 2.5c 0 5569-050 figure 62. t range and % fan speed slopes with pwm min = 20% the graphs in figure 61 assume that the fan starts from 0% pwm duty cycle. clearly, the minimum pwm duty cycle, pwm min , needs to be factored in to see how the loop actually performs in the system. figure 62 shows how t range is affected when the pwm min value is set to 20%. it can be seen that the fan runs about 45% fan speed when the temperature exceeds t min . example: determining t range for each temperature channel the following example shows how the different t min and t range settings can be applied to three different thermal zones. in this example, the following t range values apply: t range = 80c for ambient temperature t range = 53.3c for cpu temperature t range = 40c for vrm temperature this example uses the mux configuration described in the step 1configuring the mux section. both cpu temperature and vrm temperature drive the cpu fan connected to pwm1. ambient temperature drives the front chassis fan and rear chassis fan connected to pwm2 and pwm3. the front chassis fan is configured to run at pwm min = 20%. the rear chassis fan is configured to run at pwm min = 30%. the cpu fan is configured to run at pwm min = 10%. note on 4-wire fans the control range for 4-wire fans is much wider than that of 2-wire or 3-wire fans. in many cases, 4-wire fans can start with a pwm drive of as little as 20%.
adt7462 rev. a | page 45 of 92 temperature above t min 0 10203040 100 50 60 70 80 90 0 pwm duty cycle (%) 10 20 30 40 50 60 70 80 90 100 temperature above t min 0 fan speed (% max rpm) 10 20 30 40 50 60 70 80 90 100 0 10203040 100 50 60 70 80 90 05569-051 figure 63. t range and % fan speed slopes for vrm, ambient, and cpu temperature channels step 6t therm for temperature channels t therm is the absolute maximum temperature allowed on a temperature channel. above this temperature, a component such as the cpu or vrm might be operating beyond its safe operating limit. when the measured temperature exceeds t therm , all fans are driven at 100% pwm duty cycle (full speed) to provide critical system cooling. the fans remain running at 100% until the temperature drops below t therm minus hysteresis, where hysteresis is the number programmed into local/remote 1 hysteresis register 0x54 and remote 2/remote 3 hysteresis register 0x55. the default hysteresis value is 4c. the t therm limit should be considered as the maximum worst- case operating temperature of the system. because exceeding any t therm limit runs all fans at 100%, it has very negative acoustic effects. ultimately, this limit should be set up as a fail- safe, and it must not be exceeded under normal system operating conditions. note that the t therm limits cannot be masked, and they affect the fan speed no matter how the automatic fan control settings are configured. this allows some flexibility because a t range value can be selected based on its slope, while a hard limit (such as 70c), can be programmed as t max (the temperature at which the fan reaches full speed) by setting t therm to that limit (for example, 70c). therm registers register 0x4c, local therm1 temperature limit = 0xa4 (100c default) register 0x4d, remote 1 therm1 temperature limit = 0xa4 (100c default) register 0x4e, remote 2 therm1 temperature limit = 0xa4 (100c default) register 0x4f remote 3 therm1 temperature limit = 0xa4 (100c default) register 0x50, local therm2 temperature limit = 0xa4 (100c default) register 0x51, remote 1 therm2 temperature limit = 0xa4 (100c default) register 0x52, remote 2 therm2 temperature limit = 0xa4 (100c default) register 0x53 remote 3 therm2 temperature limit = 0xa4 (100c default) hysteresis registers register 0x54, local/remote 1 temperature hysteresis register bits [7:4], local temperature hysteresis (4c default) bits [3:0], remote 1 temperature hysteresis (4c default) register 0x55, remote 2/remote 3 temperature hysteresis register bits [7:4], remote 2 temperature hysteresis (4c default) bits [3:0], remote 3 temperature hysteresis (4c default) because each hysteresis setting is four bits, hysteresis values are programmable from 1c to 15c. it is not recommended that hysteresis values ever be programmed to 0c, because this value disables hysteresis. in effect, this value causes the fans to cycle between normal speed and 100% speed, creating unsettling acoustic noise.
adt7462 rev. a | page 46 of 92 t min p w m d u t y c y c l e 0% 100% t therm t range hysteresis 05569-052 figure 64. how t therm relates to automatic fan control step 7t hyst for temperature channels t hyst is the amount of extra cooling a fan provides after the temperature measured has dropped back below t min before the fan turns off. the premise for temperature hysteresis (t hyst ) is that without it, the fan would merely chatter or cycle on and off regularly whenever the temperature hovers near the t min setting. the t hyst value chosen determines the amount of time needed for the system to cool down or heat up as the fan is turning on and off. values of hysteresis are programmable in the range of 1c to 15c. larger values of t hyst prevent the fans from chattering on and off. the t hyst default value is set at 4c. hysteresis register register 0x60, bits [3:0] local hys register 0x61, bits [3:0] remote 1 hys register 0x62, bits [3:0] remote 2 hys register 0x63, bits [3:0] remote 3 hys in some applications, it is required that fans not turn off below t min but remain running at pwm min . bits [1:0] of the pwm1, pwm2 frequency register (0x25) and the pwm3, pwm4 frequency register (0x26) allow the fans to be turned off or to be kept spinning below t min . if the fans are always on, the t hyst value has no effect on the fan when the temperature drops below t min . t min p w m d u t y c y c l e 0% 100% t range t therm t hyst 05569-053 figure 65. t hyst value applies to fan on/off hysteresis dynamic t min control mode in addition to the automatic fan speed control mode described in the automatic fan control overview section, the adt7462 has a mode that extends the ba sic automatic fan speed control loop. dynamic t min control allows the adt7462 to intelligently adapt the systems cooling solution for best system performance or lowest possible system acoustics, depending on user or design requirements. use of dynamic t min control alleviates the need to design for worst-case conditions and significantly reduces system design and validation time. designing for worst-case conditions system design must always allow for worst-case conditions. in pc design, the worst-case conditions include, but are not limited to, the following: ? worst-case altitude a computer can be operated at different altitudes. altitude affects the relative air density, which alters the effectiveness of the fan cooling solution. for example, when comparing 40c air temperature at 10,000 feet to 20c air temperature at sea level, relative air density is increased by 40%. this means that the fan can spin 40% slower and make less noise at sea level than at 10,000 feet while keeping the system at the same temperature at both locations. ? worst-c as e fan due to manufacturing tolerances, fan speeds in rpm are normally quoted with a tolerance of 20%. the designer must assume that the fan rpm can be 20% below tolerance. this translates to reduced system airflow and elevated system temperature. note that fans 20% out of tolerance can negatively impact system acoustics because they run faster and generate more noise. ? worst-case chassis airflow the same motherboard can be used in a number of different chassis configurations. the design of the chassis and the physical location of fans and components determine the systems thermal characteristics. moreover, for a given chassis, the addition of add-in cards, cables, or other system configuration options can alter the system airflow and reduce the effectiveness of the system cooling solution. the cooling solution can also be inadvertently altered by the end user. (for example, placing a computer against a wall can block the air ducts and reduce system airflow.) fan i/o cards poor cpu airflow vents power supply cpu drive bays good venting = good air exchange poor venting = poor air exchange vents fan i/o cards good cpu airflow fan v ents power supply cpu drive bays 0 5569-054 figure 66. chassis airflow issues
adt7462 rev. a | page 47 of 92 ? worst-case processor power consumption this data sheet maximum does not necessarily reflect the true processor power consumption. designing for worst- case cpu power consumption can result in a processor becoming overcooled (generating excess system noise). ? worst-case peripheral power consumption the tendency is to design to data sheet maximums for peripheral components (again overcooling the system). ? worst-case assembly every system manufactured is unique because of manufac- turing variations. heat sinks may be loose fitting or slightly misaligned. too much or too little thermal grease may be used. variations in application pressure for thermal interface material can affect the efficiency of the thermal solution. accounting for manufacturing variations in every system is difficult; therefore, the system must be designed for the worst case. substrate heat sink thermal interface material integrated heat spreader epoxy thermal interface material processor t a t j ca sa tims ctim timc jtim cs t c t tim t s t tim ja 05569-055 figure 67. thermal model although a design usually accounts for worst-case conditions in all these cases, the actual system is almost never operated at worst-case conditions. the alternative to designing for the worst case is to use the dynamic t min control function. dynamic t min control overview dynamic t min control mode builds upon the basic automatic fan control loop by adjusting the t min value based on system performance and measured temperature. this is important because, instead of designing for the worst case, the system thermals can be defined as operating zones. the adt7462 can self-adjust its fan control loop to maintain either an operating zone temperature or a system target temperature. for example, it can be specified that ambient temperature in a system be maintained at 50c. if the temperature is below 50c, the fans might not need to run or might run very slowly. if the temperature is higher than 50c, the fans need to throttle up. the challenge presented by any thermal design is finding the right settings to suit the systems fan control solution. this can involve designing for the worst case, followed by weeks of system thermal characterization and, finally, fan acoustic optimization (for psycho-acoustic reasons). obtaining the greatest benefit from the automatic fan control mode involves characterizing the system to find the best t min and t range settings for the control loop and the best pwm min value for the quietest fan speed setting. using the adt7462 dynamic t min control mode, however, shortens the characteriza- tion time and alleviates tweaking the control loop settings, because the device can self-adjust during system operation. dynamic t min control mode is operated by specifying the operating zone temperatures required for the system. remote 1 and remote 2 channels have dedicated operating point registers. this allows the system thermal solution to be broken down into distinct thermal zones. for example, cpu operating temperature is 70c, vrm operating temperature is 80c, and ambient operating temperature is 50c. the adt7462 dynamically alters the control solution to maintain each zone temperature as close as possible to its target operating point. figure 68 shows an overview of the parameters that affect the operation of the dynamic t min control loop. pwm duty cycl e t low t min operating point t high t range temperature t therm 05569-056 figure 68. dynamic t min control loop table 28 provides a brief description of each parameter. table 28. t min control loop parameters parameter description t low if the temperature drops below the t low limit, an error flag is set in a status register and an smbalert interrupt can be generated. t high if the temperature exceeds the t high limit, an error flag is set in a status register and an smbalert interrupt can be generated. t min the temperature at which the fan turns on under automatic fan speed control. operating point the maximum target temperature for a particular temperature zone. the system attempts to maintain system temperature around the operating point by adjusting the t min parameter of the control loop. t therm if the temperature exceeds this critical limit, the fans can be run at 100% for maximum cooling. t range programs the pwm duty cycle vs. temperature control slope.
adt7462 rev. a | page 48 of 92 dynamic t min control programming because the dynamic t min control mode is a basic extension of the automatic fan control mode, the automatic fan control mode parameters should be programmed first (see step 1configuring the mux through step 8operating points for temperature channels). then proceed with dynamic t min control mode programming. step 8operating points for temperature channels the operating point for each temperature channel is the optimal temperature for that thermal zone. the hotter each zone is allowed to be, the quieter the system, because the fans are not required to run as fast. the ad t7462 increases or decreases fan speeds as necessary to maintain the operating point temperature, allowing for system-to-system variation and removing the need for worst-case design. if a sensible operating point value is chosen, any t min value can be selected in the system characteri- zation. if the t min value is too low, the fans run sooner than required, and the temperature is below the operating point. in response, the adt7462 increases t min to keep the fans off longer and to allow the temperature zone to get closer to the operating point. likewise, too high a t min value causes the operating point to be exceeded, and in turn, the adt7462 reduces t min to turn the fans on sooner to cool the system. programming the operat ing point registers there are two operating point registers, one for the remote 1 temperature channel and one for the remote 2 temperature channel. these 8-bit registers allow the operating point temperatures to be programmed with 1c resolution. operating point registers register 0x5a, remote 1 operating point = 0xa4 (100c default) register 0x5b, remote 2 operating point = 0xa4 (100c default) operating point hysteresis register the operating point hysteresis register sets the value below the operating point at which t min begins to reduce. register 0x64, bits [7:4] operating point hysteresis = 0x40 (4c default) step 9high and low limits for temperature channels the low limit defines the temperature at which the t min value starts to be increased, if temperature falls below this value. this has the net effect of reducing the fan speed, allowing the system to get hotter. an interrupt can be generated when the tempera- ture drops below the low limit. the high limit should be set above the operating point but below the critical therm point. an interrupt can be generated when the temperature rises above the high limit. how dynamic t min control works the basic operation of dynamic t min control is as follows: 1. set the target temperature for the temperature zone, which could be, for example, the remote 1 thermal diode. this value is programmed to the remote 1 operating point register. 2. as the temperature in that zone rises toward and exceeds the operating point temperature minus hysteresis, t min is reduced and fan speed increases. 3. as the temperature drops below the low limit value, t min is increased and the fan speed is reduced. short cycle and long cycle the adt7462 implements two loops: a short (or decrease) cycle and a long (or increase) cycle. the short cycle takes place every n monitoring cycles. the long cycle takes place every 2 n monitoring cycles. the value of n is programmable for each temperature channel. the bits are located at the following register locations. dynamic t min control register 2 (0x0c) bits [2:0] (cyr1) = remote 1 bits [5:3] (cyr2) = remote 2 table 29. cycle bit assignments code short cycle duration long cycle duration 000 8 cycles 1 sec 16 cycles 2 sec 001 16 cycles 2 sec 32 cycles 4 sec 010 32 cycles 4 sec 64 cycles 8 sec 011 64 cycles 8 sec 128 cycles 16 sec 100 128 cycles 16 sec 256 cycles 32 sec 101 256 cycles 32 sec 512 cycles 64 sec 110 512 cycles 64 sec 1024 cycles 128 sec 111 1024 cycles 128 sec 2048 cycles 256 sec the cycle time must be chosen carefully. a long cycle time means that t min is updated less often. if a system has very fast temperature transients, the dynamic t min control loop is always lagging. if a cycle time that is too short is chosen, the full benefit of changing t min is not realized and t min needs to change again on the next cycle. in effect, it is overshooting. it is necessary to carry out some calibration to identify the most suitable response time. figure 69 shows the steps taken during the short cycle.
adt7462 rev. a | page 49 of 92 is t1(n) ? t1(n ? 1) = 0.5 ? 0.75c is t1(n) ? t1(n ? 1) = 1.0 ? 1.75c is t1(n) ? t1(n ? 1) > 2.0c is t1(n) > (op1 ? hys) yes is t1(n) ? t1(n ? 1) 0.25c do nothing (system cooling is off or constant) yes no no do nothing wait n monitoring cycles previous temperature measurement t1 (n ? 1) current temperature measurement t1(n) operating point temperature op1 decrease t min by 1c decrease t min by 2c decrease t min by 4c 05569-058 figure 69. short cycle steps figure 70 shows the steps taken during the long cycle. wait 2n monitoring cycles is t1(n) < low temp limit and t min < high temp limit and t min < op1 and t1(n) > t min is t1(n) > op1 yes increase t min by 1c yes no no decrease t min by 1c current temperature measurement t1(n) operating point temperature op1 do not change 05569-059 figure 70. long cycle steps the following examples illustrate some of the circumstances that may cause t min to increase, decrease, or stay the same. example 1: normal operation, no t min adjustment 1. if the measured temperature never exceeds the programmed operating point minus the hysteresis temperature, t min is not adjusted; that is, it remains at its current setting. 2. if the measured temperature never drops below the low temperature limit, t min is not adjusted. t min t herm limit operating point high temp limit low temp limit actual temp hysteresis 0 5569-060 figure 71. temperature between the operating point and the low temperature limit because neither the operating point minus the hysteresis temperature nor the low temperature limit has been exceeded, the t min value is not adjusted, and the fan runs at a speed determined by the fixed t min and t range values defined in the automatic fan speed control mode. example 2: operating point exceeded, t min reduced when the measured temperature is below the operating point temperature minus the hysteresis, t min remains the same. once the temperature exceeds the operating temperature minus the hysteresis (op ? hyst), t min starts to decrease as illustrated in figure 72. this occurs during the short cycle (see figure 69). the rate at which t min decreases depends on the programmed value of n . it also depends on how much the temperature has increased between this monitoring cycle and the last monitoring cycle; that is, if the temperature has increased by 1c, then t min is reduced by 2c. decreasing t min has the effect of increasing the fan speed, thus providing more cooling to the system. if the temperature is slowly increasing only in the range (op ? hyst), that is, 0.25c per short monitoring cycle, then t min does not decrease. this allows small changes in temperature in the desired operating zone without changing t min . the long cycle makes no change to t min in the tempera- ture range (op ? hyst), because the temperature has not exceeded the operating temperature. when the temperature exceeds the operating temperature, the long cycle causes t min to be reduced by 1c every long cycle while the temperature remains above the operating temperature. this takes place in addition to the decrease in t min that would occur due to the short cycle. in figure 71, because the temperature is increasing at a rate 0.25c per short cycle, no reduction in t min takes place during the short cycle. when the temperature falls below the operating temperature, t min stays the same. even when the temperature starts to increase slowly, t min stays the same, because the temperature increases at a rate of 0.25c per cycle.
adt7462 rev. a | page 50 of 92 t min therm limit operating point high temp limit low temp limit hysteresis decrease here due to short cycle only t1(n) ? t1 (n ? 1) = 0.5c or0.75c=>t min decreases by 1c every short cycle decrease here due to long cycle only t1(n) ? t1 (n ? 1) 0.25c and t1(n) > op = > t min decreases by 1c every long cycle no change in t min here due to any cycle because t1(n) ? t1 (n ? 1) 0.25c and t1(n) < op = > t min stays the same actual temp 05569-061 figure 72. effect of exceeding operatin g point minus hysteresis temperature example 3: temperature below low limit, t min increased when the temperature drops below the low temperature limit, t min may increase, as shown in figure 73. increasing t min has the effect of running the fan more slowly and, therefore, more quietly. the long cycle diagram in figure 70 shows the conditions that need to be true for t min to increase. the following is a quick summary of those conditions and the reasons they need to be true: t min may increase, if ? the measured temperature has fallen below the low temperature limit. this means the user must choose the low limit carefully. it should not be so low that the temperature never falls below it, because t min would never increase and the fans would run faster than necessary. ? t min is below the high temperature limit. t min is never allowed to increase above the high temperature limit. as a result, the high limit should be sensibly chosen, because it determines how high t min can go. ? t min is below the operating point temperature. t min should never be allowed to increase above the operating point temperature, because the fans do not switch on until the temperature rises above the operating point. ? the temperature is above t min . the dynamic t min control is turned off below t min . figure 73 shows how t min increases when the current tempera- ture is above t min and below the low temperature limit, and t min is below the high temperature limit and below the operating point. when the temperature rises above the low temperature limit, t min stays the same. t min operating point high temp limit low temp limit actual temp hysteresis therm limit 05569-062 figure 73. increasing t min for quieter operation example 4: preventing t min from reaching full scale because t min is dynamically adjusted, it is undesirable for t min to reach full scale (191c), because the fan would never switch on. as a result, t min is allowed to vary only within a specified range. ? the lowest possible value for t min is ?64c. ? t min cannot exceed the high temperature limit. ? if the temperature is below t min , the fan is switched off or is running at minimum speed, and dynamic t min control is disabled.
adt7462 rev. a | page 51 of 92 t min prevented from increasing t min o perating point high temp limit low temp limit actual temp hysteresis therm limit 05569-063 figure 74. t min adjustments limited by high temperature limit enabling dynamic t min control mode bits [1:0] of dynamic t min control register 1 (0x0b) enable/disable dynamic t min control on the temperature channels (see table 43). dynamic t min control register 1 (0x0b) bit 1 (remote 2 en) = 1 enables dynamic t min control on the remote 2 temperature channel. the chosen t min value is dynamically adjusted based on the current temperature, operating point, and high and low limits for this zone. bit 1 (remote 2 en) = 0 disables dynamic t min control. the t min value chosen is not adjusted and the channel behaves as described in the automatic fan control overview section. bit 0 (remote 1 en) = 1 enables dynamic t min control on the remote 1 temperature channel. the chosen t min value is dynamically adjusted based on the current temperature, operating point, and high and low limits for this zone. bit 0 (remote 1 en) = 0 disables dynamic t min control. the t min value chosen is not adjusted, and the channel behaves as described in the automatic fan control overview section. step 10monitoring therm using the operating point limit ensures that the dynamic t min control mode is operating in the best possible acoustic position, while ensuring that the temperature never exceeds the maxi- mum operating temperature. using the operating point limit allows t min to be independent of system-level issues because of its self-corrective nature. in pc design, the operating point for the chassis is usually the worst-case internal chassis temperature. the optimal operating point for the processor is determined by monitoring the thermal monitor in the intel pentium 4 proces- sor. to do this, the prochot output of the pentium 4 is connected to the therm input of the adt7462. the operating point for the processor can be determined by allowing the current temperature to be copied to the operating point register when the prochot output pulls the therm input low on the adt7462. this gives the maximum temperature at which the pentium 4 can run before clock modulation occurs. enabling the therm trip point as the operating point bits [5:2] of dynamic t min control register 1 (0x0b) enable/disable therm monitoring to program the operating point. table 43 details how the remote temperatures can be copied into the operating point registers on a therm assertion. setting these bits to 1 uses the remote temperature as the operating point temperature, overwriting the programmed operating point value in the event of a therm assertion. setting these bits to 0 ignores a therm assertion, and the operating point register remains at the programmed value. enhancing system acoustics automatic fan speed control mode reacts instantaneously to changes in temperature; that is, the pwm duty cycle responds immediately to temperature change. any impulses in temperature can cause an impulse in fan noise. for psycho-acoustic reasons, the adt7462 can prevent the pwm output from reacting instantaneously to temperature changes. enhanced acoustic mode controls the maximum change in pwm duty cycle at a given time. the objective is to prevent the fan from cycling up and down, annoying the user. acoustic enhancement mode overview figure 75 gives a top-level overview of the automatic fan control circuitry on the adt7462 and shows where acoustic enhancement fits in. acoustic enhancement is intended as a postdesign tweak made by a system or mechanical engineer evaluating best set- tings for the system. having determined the optimal settings for the thermal solution, the engineer can adjust the system acoustics. the goal is to implement a system that is acoustically pleasing without causing user annoyance due to fan cycling. it is important to realize that although a system might pass an acoustic noise requirement specification (for example, 36 db), if the fan is annoying, it fails the consumer test.
adt7462 rev. a | page 52 of 92 a coustic enhancement rear chassis front chassis cpu fan sink local = vrm temp pwm1 pwm2 tach1 tach2 tach3 pwm3 remote 1 = ambient temp remote 2 = cpu temp mux thermal calibration 0% t min t range thermal calibration 100% 0% t min t range thermal calibration 100% 0% t min t range tachometer 1 measurement pwm config pwm min ramp control (acoustic enhancement) pwm generator tachometer 2 measurement pwm config pwm min ramp control (acoustic enhancement) pwm generator tachometer 3 and 4 measurement pwm config pwm min ramp control (acoustic enhancement) pwm generator 100% 05569-064 figure 75. acoustic enhancement smoothes fan sp eed variations under automatic fan speed control approaches to system acoustic enhancement there are two different approaches to implementing system acoustic enhancement: temperature-centric and fan-centric. the temperature-centric approach involves smoothing transient temperatures as they are measured by a temperature source (for example, remote 1 temperature). the temperature values used to calculate the pwm duty cycle values are smoothed, reducing fan speed variation. however, this approach causes an inherent delay in updating fan speed and causes the thermal characteristics of the system to change. it also causes the system fans to stay on longer than necessary, because the fans reaction is merely delayed. the user has no control over noise from different fans driven by the same temperature source. consider, for example, a system in which control of a cpu cooler fan (on pwm1) and a chassis fan (on pwm2) uses remote 1 temperature. because the remote 1 temperature is smoothed, both fans are updated at exactly the same rate. if the chassis fan is much louder than the cpu fan, there is no way to improve its acoustics without changing the thermal solution of the cpu cooling fan. the fan-centric approach to system acoustic enhancement controls the pwm duty cycle, driving the fan at a fixed rate (for example, 6%). each time the pwm duty cycle is updated, it is incremented by a fixed 6%. as a result, the fan ramps smoothly to its newly calculated speed. if the temperature starts to drop, the pwm duty cycle immediately decreases by 6% at every update. therefore, the fan ramps smoothly up or down without inherent system delay. consider, for example, controlling the same cpu cooler fan (on pwm1) and chassis fan (on pwm2) using remote 1 temperature. the t min and t range settings have already been defined in automatic fan speed control mode; that is, thermal characteri- zation of the control loop has been optimized. the chassis fan is noisier than the cpu cooling fan. using the fan-centric approach, pwm2 can be placed into acoustic enhancement mode independently of pwm1. the acoustics of the chassis fan can, therefore, be adjusted without affecting the acoustic behavior of the cpu cooling fan, even though both fans are controlled by remote 1 temperature. the fan-centric approach is how acoustic enhancement works on the adt7462. enabling acoustic enhancem ent for each pwm output enhanced acoustics register 1 (0x1a) bit 0 (en1) = 1 enables acoustic enhancement on pwm1 output. bit 1 (en2) = 1 enables acoustic enhancement on pwm2 output. enhanced acoustics register 2 (0x1b) bit 0 (en3) = 1 enables acoustic enhancement on pwm3 output. bit 1 (en4) = 1 enables acoustic enhancement on pwm4 output.
adt7462 rev. a | page 53 of 92 effect of ramp rate on enhanced acoustic mode the pwm signal driving the fan has a period, t, given by the pwm drive frequency, f, because t = 1/f. for a given pwm period, t, the pwm period is subdivided into 255 equal time slots. one time slot corresponds to the smallest possible incre- ment in the pwm duty cycle. a pwm signal of 33% duty cycle is, therefore, high for 1/3 255 time slots and low for 2/3 255 time slots. therefore, a 33% pwm duty cycle corresponds to a signal that is high for 85 time slots and low for 170 time slots. 170 time slots 85 time slots pwm output (one period) =255timeslots pwm_out 33% duty cycle 05569-065 figure 76. 33% pwm duty cycle represented in time slots the ramp rates in the enhanced acoustics mode are selectable from 1 to 8. the ramp rates are discrete time slots. for example, if the ramp rate is 8, then eight time slots are added to the pwm high duty cycle each time the pwm duty cycle needs to be increased. if the pwm duty cycle value needs to be decreased, it is decreased by eight time slots. figure 77 shows how the enhanced acoustics mode algorithm operates. read temperature calculate new pwm duty cycle is new pwm value > previous value? increment previous pwm value by ramp rate yes no decrement previous pwm value by ramp rate 05569-066 figure 77. enhanced acoustics mode algorithm the enhanced acoustics mode algorithm calculates a new pwm duty cycle based on the temperature measured. if the new pwm duty cycle value is greater than the previous pwm value, the previous pwm duty cycle value is incremented by either 1, 2, 3, 5, 8, 12, 24, or 48 time slots, depending on the settings of the enhanced acoustics registers. if the new pwm duty cycle value is less than the previous pwm value, the previous pwm duty cycle is decremented by 1, 2, 3, 5, 8, 12, 24, or 48 time slots. each time the pwm duty cycle is incremented or decremented, its value is stored as the previous pwm duty cycle for the next comparison. a ramp rate of 1 corresponds to one time slot, which is 1/255 of the pwm period. in enhanced acoustics mode, incrementing or decrementing by 1 changes the pwm output by 1/255 100%. step 11ramp rate for acoustic enhancement the optimal ramp rate for acoustic enhancement can be found through system characterization after the thermal optimization has been finished. the effect of each ramp rate should be logged, if possible, to determine the best setting for a given solution. enhanced acoustics register 1 (0x1a) bits [4:2] rr1 select the ramp rate for pwm1. 000 = 1 time slot = 35 seconds 001 = 2 time slots = 17.6 seconds 010 = 3 time slots = 11.8 seconds 011 = 5 time slots = 7 seconds 100 = 8 time slots = 4.4 seconds 101 = 12 time slots = 3 seconds 110 = 24 time slots = 1.6 seconds 111 = 48 time slots = 0.8 seconds bits [7:5] rr2 s elect the ramp rate for pwm2. 000 = 1 time slot = 35 seconds 001 = 2 time slots = 17.6 seconds 010 = 3 time slots = 11.8 seconds 011 = 5 time slots = 7 seconds 100 = 8 time slots = 4.4 seconds 101 = 12 time slots = 3 seconds 110 = 24 time slots = 1.6 seconds 111 = 48 time slots = 0.8 seconds enhanced acoustics register 2 (0x1b) bits [4:2] rr3 s elect the ramp rate for pwm3. 000 = 1 time slot = 35 seconds 001 = 2 time slots = 17.6 seconds 010 = 3 time slots = 11.8 seconds 011 = 5 time slots = 7 seconds 100 = 8 time slots = 4.4 seconds 101 = 12 time slots = 3 seconds 110 = 24 time slots = 1.6 seconds 111 = 48 time slots = 0.8 seconds bits [7:5] rr4 select the ramp rate for pwm4. 000 = 1 time slot = 35 seconds 001 = 2 time slots = 17.6 seconds 010 = 3 time slots = 11.8 seconds 011 = 5 time slots = 7 seconds 100 = 8 time slots = 4.4 seconds 101 = 12 time slots = 3 seconds 110 = 24 time slots = 1.6 seconds 111 = 48 time slots = 0.8 seconds
adt7462 rev. a | page 54 of 92 another way to view the ramp rates is to measure the time it takes for the pwm output to ramp up from 0% to 100% duty cycle for an instantaneous change in temperature. this can be tested by putting the adt7462 into manual mode and changing the pwm output from 0% to 100% pwm duty cycle. the pwm output takes 35 seconds to reach 100% when a ramp rate of one time slot is selected. figure 78 shows remote temperature plotted against pwm duty cycle for enhanced acoustics mode. the ramp rate is set to 48, which corresponds to the fastest ramp rate. assume that a new temperature reading is available every 115 ms. with these settings, it takes approximately 0.76 seconds to go from 33% duty cycle to 100% duty cycle (full speed). even though the temperature increases very rapidly, the fan ramps up to full speed gradually. time (s) 140 00.76 120 100 80 60 40 20 0 120 100 80 60 40 20 0 r temp (c) pwm cycle (%) 05569-067 figure 78. enhanced acoustics mode with ramp rate = 48 figure 79 shows how changing the ramp rate from 48 to 8 affects the control loop. the overall response of the fan is slower. because the ramp rate is reduced, it takes longer for the fan to achieve full running speed. in this case, it takes approximately 4.4 seconds for the fan to reach full speed. time (s) 120 0 4.4 140 120 100 80 60 40 0 20 100 80 60 40 20 0 r temp (c) pwm duty cycle (%) 05569-068 figure 79. enhanced acoustics mode with ramp rate = 8 figure 80 shows the pwm output response for a ramp rate of 2. in this instance, the fan takes about 17.6 seconds to reach full running speed. time (s) 140 0 17.6 120 100 80 60 40 20 0 120 100 80 60 40 20 0 r temp (c) pwm duty cycle (%) 0 5569-069 figure 80. enhanced acoustics mode with ramp rate = 2 figure 81 shows how the control loop reacts to temperature with the slowest ramp rate. the ramp rate is set to 1, while all other control parameters remain the same. with the slowest ramp rate selected, it takes 35 seconds for the fan to reach full speed. time (s) 0 35 120 100 80 60 40 20 0 140 120 100 80 60 40 20 0 r temp (c) pwm duty cycle (%) 05569-070 figure 81. enhanced acoustics mode with ramp rate = 1 as figure 78 to figure 81 show, the rate at which the fan reacts to temperature change is dependent on the ramp rate selected in the enhanced acoustics registers. the higher the ramp rate, the faster the fan reaches the newly calculated fan speed. figure 82 shows the behavior of the pwm output as temperature varies. as the temperature increases, the fan speed ramps up. small drops in temperature do not affect the ramp-up function, because the newly calculated fan speed is still higher than the previous pwm value. enhanced acoustics mode allows the pwm output to be made less sensitive to temperature variations. this is dependent on the ramp rate selected and programmed into the enhanced acoustics registers.
adt7462 rev. a | page 55 of 92 9 0 8 0 7 0 6 0 5 0 4 0 0 3 0 2 0 10 pwm duty cycle (%) r temp (c) 05569-071 figure 82. how fan reacts to temperature variations in enhanced acoustics mode slower ramp rates the adt7462 can be programmed for much longer ramp times by slowing the ramp rates. each ramp rate can be slowed by a factor of 4. pwm1 configuration register (0x21) pwm2 configuration register (0x22) pwm3 configuration register (0x23) pwm4 configuration register (0x24) setting bit 3 (the slow bit) to 1 in the pwm1 to pwm4 configuration registers slows the ramp rate for pwm1 to pwm4 by 4. fan freewheeling test mode the fan freewheeling test mode is intended to diagnose whether fans connected to the adt7462 are working properly. it is particularly useful where fans coupled in the duct can affect the airflow of another fan. if one fan has failed, it may not be apparent, because moving air from other fans can cause air to flow through the faulty fan, which in turn can cause the faulty fan to rotate. the fan freewheeling test is most useful in a system using primary and redundant setup. in such a system, the following setup is recommended. the primary fans are fan 1, fan 2, fan 3, and fan 4. the redundant fans are fan 5, fan 6, fan 7, and fan 8. in this setup, each primary and redundant fan can be driven separately because they are driven by different pwms. pwm 1 pwm 2 pwm 3 pwm 4 tach cct 1 tach cct 2 tach cct 3 tach cct 4 fan 1 fan 2 fan 3 fan 4 fan 5 fan 6 fan 7 fan 8 0 5569-072 figure 83. fan freewheeling test mode setup the freewheeling test procedure is as follows: 1. pwm1 and pwm2 go to full speed, and pwm3 and pwm4 are switched off. 2. after the spin-up time of pwm1 and pwm2 has elapsed, the speed of fan 1, fan 2, fan 3, and fan 4 is measured. 3. after the speed of fan 1 and fan 2 is measured, pwm1 is switched off and pwm3 is spun up. after the spin-up time for pwm3 has elapsed, the speed of fan 5 and fan 6 is measured. 4. after the speed of fan 3 and fan 4 is measured, pwm2 is switched off and pwm4 is switched on. after the spin-up time of pwm4 has elapsed, the speed of fan 7 and fan 8 is measured. 5. after the speed of all eight fans has been measured, the tach and pwm configurations return to their previous values. a. fans must be in continuous mode for the freewheeling test; that is, the dc bits must be set (register 0x08). b. to enable the freewheeling test, set the freewheeling test enable register (0x1e) to a nonzero value. set bit 0 = 1 to enable the freewheeling test for fan 1, and set bit 1 for fan 2, all the way to bit 7 for fan 8. the freewheeling test enable register should be pro- grammed after the fans present register is programmed. if the fans present register is not programmed first, then the values in the two registers do not match, and the adt7462 assumes that a fan is missing. the following registers must be programmed for the fan freewheeling test: fans present register (0x1d) set bit 0 to 1 when a fan is connected to tach1. set bit 1 to 1 when a fan is connected to tach2. set bit 2 to 1 when a fan is connected to tach3. set bit 3 to 1 when a fan is connected to tach4. set bit 4 to 1 when a fan is connected to tach5. set bit 5 to 1 when a fan is connected to tach6. set bit 6 to 1 when a fan is connected to tach7. set bit 7 to 1 when a fan is connected to tach8. fan freewheeling test enable register (0x1e) set bit 0 to 1 to enable the freewheeling test for fan 1. set bit 1 to 1 to enable the freewheeling test for fan 2. set bit 2 to 1 to enable the freewheeling test for fan 3. set bit 3 to 1 to enable the freewheeling test for fan 4. set bit 4 to 1 to enable the freewheeling test for fan 5. set bit 5 to 1 to enable the freewheeling test for fan 6. set bit 6 to 1 to enable the freewheeling test for fan 7. set bit 7 to 1 to enable the freewheeling test for fan 8. fan freewheeling test register (0x1c) both the fans present register (0x1d) and the freewheeling test enable register (0x1e) should be programmed before setting the relevant bits in the fan freewheeling test register (0x1c). the host fan status register (0xbd) should be read directly after completion of the test.
adt7462 rev. a | page 56 of 92 therm i/o operation this section describes the operation of therm1 and therm2 . pin 28 and pin 29 can both be configured as therm inputs or outputs. therm output therm is not enabled as an output by default on power-up, but it can be enabled by setting the appropriate bits in register 0x0e ( therm1 configuration register) and register 0x0f ( therm2 configuration register). therm1 and therm2 can be config- ured to assert whenever a specific channel exceeds the specified therm limit (see table 30). table 30. therm output channel select and limits configuration limit registers channel enable therm1 , register 0x0e therm2 , register 0x0f therm1 therm2 local bit 1 = 1 bit 1 = 1 0x4c 0x50 remote 1 bit 2 = 1 bit 2 = 1 0x4d 0x51 remote 2 bit 3 = 1 bit 3 = 1 0x4e 0x52 remote 3 bit 4 = 1 bit 4 = 1 0x4f 0x53 as an output, therm is asserted low to signal that the measured therm temperature has exceeded preprogrammed therm temperature limits. the output is automatically pulled high again when the temperature falls below the ( therm ? hysteresis) limit. the value of hysteresis for each channel is programmable in register 0x54 and register 0x55, where 1 lsb = 1c, and the maximum hysteresis for each channel is 15c. setting the therm boost bits, bit 0 and bit 1, to logic 0 (default setting) in the therm configuration register (0x0d), sets the fans to full speed on an internal therm event. therm input to conf igure therm as an input, the therm1 _timer_enable (t1te) bit (bit 0) in the therm1 configuration register (0x0e) and the therm2 _timer_enable (t2te) bit (bit 0) in the therm2 configuration register (0x0f) must be set to logic 1. the adt7462 can then be used to detect when the therm pins are asserted low. the therm pins can be connected to a trip point temperature sensor or to the prochot output of a cpu. with processor core voltages reducing all the time, the threshold for the agtl+ prochot output is also reduced as new processors become available. because the therm input is typically an agtl+ input, the thresholds can be referenced to v ccp . by setting bit 4 of configuration register 3 (0x03) to 1, the therm threshold is 2/3 v ccp , the correct threshold for an agtl+ signal. the therm assert bits in host thermal status register 2 (0xb9) are set to logic 1 whenever the therm input is asserted low. the therm state bits in host thermal status register 2 (0xb9) indicate that a high-to-low transition has taken place on the therm pin. 100c 90c 80c 70c 60c 50c 40c therm therm limit therm limit?hysteresis t emper a ture high temp limit 1 3 2 4 reset by master alert 05569-073 figure 84. therm behavior
adt7462 rev. a | page 57 of 92 therm timer the adt7462 can also measure assertion times on the therm inputs as a percentage of a timer window. the timer window for the therm1 input is programmed using bits [4:2] of the therm configuration register (0x0d). the timer window for the therm2 input is programmed using bits [7:5] of the therm configuration register (0x0d). values from 0.25 sec to 8 sec are programmable (see table 31). table 31. therm timer window code therm timer window 000 0.25 sec 001 0.5 sec 010 1 sec 011 2 sec 100 4 sec 101 8 sec 110 8 sec 111 8 sec the assertion time as a percentage of the timer window is stored in the therm % on-time registers. this is a cumulative sum of the percentage of time during the therm timer win- dow that therm is asserted. the % on-time and associated timer limit registers are listed in table 32. table 32. therm on-time and timer limit register channel % on-time register % timer limit register therm1 0xae 0x80 therm2 0xaf 0x81 when the measured percentage exceeds the corresponding per- centage limit, the t1% bit in host thermal status register 2 (0xb9) is asserted, and an alert is generated (that is, if the mask bit is not set). if the limit is set to 0x00, an alert is generated on the first assertion. if the limit is set to 0xff, an alert is never generated because 0xff corresponds to the therm input being asserted all the time. when therm is configured as an input only, setting bits [4:1] of the therm zone in the therm1 configuration register (0x0e) and the therm2 configuration register (0x0f) allows pin 28/pin 29 to operate as an i/o. therm timer limit register the therm timer limit is programmed to register 0x80 and register 0x81. if therm is asserted for longer than the programmed percentage limit, then an alert is generated. the limit is programmed as a percentage of the chosen therm timer window. example the therm timer window is eight seconds, and an alert should be generated if therm is asserted for more than one second. % 5 . 12 100 8 1 % = = limit the therm timer limit register is an 8-bit register. 0x00 = 0%; 0xff = 100% therefore, 1 lsb = 0.39% 00100000 20 x 0 decimal 32 % 39 . 0 % 5 . 12 = = = when the time window has elapsed, if the therm limit has been exceeded, then an alert is generated.
adt7462 rev. a | page 58 of 92 general-purpose i/o pins the adt7462 has eight open-drain gpio pins. gpio1 to gpio4 can be configured to enable event driven outputs (edos), and gpio5 and gpio6 can act as edos, if the edo functionality is enabled. two other gpios (gpio7 and gpio8) are standard gpio pins that are dedicated to general-purpose logic input/output. each gpio pin has five data bits associated with it: three bits in a gpio configuration register (0x09 and 0x0a), one in the gpio status register (0xbf), and one in the gpio mask register (0x36). setting a direction bit to 1 in a gpio configuration register makes the corresponding gpio pin an output. clearing the direction bit to 0 makes the corresponding gpio pin an input. setting a polarity bit to 1 in a gpio configuration register makes the corresponding gpio pin active high. clearing the polarity bit to 0 makes the corresponding gpio pin active low. when a gpio pin is configured as an input, the corresponding bit in the gpio status register is read-only, and it is set when the input is asserted (asserted can be high or low, depending on the setting of the polarity bit). when a gpio pin is configured as an output, the corresponding bit in the gpio status register becomes read/write. setting this bit then asserts the gpio output. (again, asserted can be high or low, depending on the setting of the polarity bit.) the effect of a gpio status register bit on the alert output can be masked by setting the corresponding bit in one of the gpio mask registers. when the pin is configured as an output, the corresponding status bit is automatically masked to prevent the data written to the status bit from causing an interrupt. when configured as inputs, the gpio pins can be connected to external interrupt sources such as temperature sensors with digital output. edo circuitry the adt7462 has the added functi onality that the assertion of one of the four gpios (gpio1 to gpio4) can be used to latch one of the two edos high or low. the adt7462 has two edo event mask registers (0x37 and 0x38): one mask for each edo. see table 33 for an explanation of event mask register functionality. the polarity of the edos is set in the gpio configuration registers (0x09 and 0x0a). setting a polarity bit to 1 in one of the gpio configuration registers makes the corresponding gpio pin active high. clearing the polarity bit to 0 makes it active low. gpio1 gpio2 gpio3 gpio4 latch event mask edo (gpio5) edo (gpio6) 05569-074 figure 85. edo circuit bits [7:5] of each event mask register (0x37 and 0x38) allow the edo output to be driven high or low (depending on the polarity bit of the configuration register) and latched (depending on the edo latch bit of the configuration register), if the adt7462 detects an overtemperature, an overvoltage/undervoltage, or a fan failure condition. table 33. edo control (mask) re gister 0x37 and register 0x38 bit 7: overvoltage/ undervoltage bit 6: therm bit 5: fan fail bit 3 bit 2 bit 1 bit 0 behavior: what drives and latches output x (g = gpio) 0 = drive output x 0 = drive output x 0 = drive output x 0 0 0 0 g4 or g3 or g2 or g1 1 = ignore event 1 = ignore event 1 = ignore event 0 0 0 1 g4 or g3 or g2 0 0 1 0 g4 or g3 or g1 0 0 1 1 g4 or g3 0 1 0 0 g4 or g2 or g1 0 1 0 1 g4 or g2 0 1 1 0 g4 or g1 0 1 1 1 g4 1 0 0 0 g3 or g2 or g1 1 0 0 1 g3 or g2 1 0 1 0 g3 or g1 1 0 1 1 g3 1 1 0 0 g2 or g1 1 1 0 1 g2 1 1 1 0 g1 1 1 1 1 gpio events ignored by output x
adt7462 rev. a | page 59 of 92 2 table 33 shows that any of the four designated gpio pins can be used to set or reset either one of the two edo outputs. using this functionality, it is possible to have the adt7462 drive leds or signals based on rules. for example, if a gpio1 (power fail), a gpio2 (overcurrent), or an overtemperature condition occurs, edo1 (power supply fault led) can be latched. this does not require software handling and makes the part more autonomous. other digital inputs the adt7462 contains other specific digital inputs that can be found on pc motherboards. these inputs can be monitored and configured for actions to occur on their assertion. vr_hot inputs pin 25 and pin 26 can be configured as vr_hot inputs. these are specific digital signals from the cpu voltage regulator that indicate an overtemperature. on assertion of these inputs, the relevant status bits are set in thermal status register 2 (host register 0xb9 or bmc register 0xc1). assertion of these inputs can also be used to boost the fans to full speed, thus providing emergency cooling in the event of vr overtemperature. this is set using bit 3 (vrd1) and bit 4 (vrd2) of configuration register 2 (0x02). there is also an associated mask bit in register 0x31 to mask the assertion of these inputs from the alert output. scsi_term inputs pin 16 and pin 20 can be configured as scsi_term inputs. an assertion on the scsi_term is recorded in bit 4 and bit 5 of host digital status register (0xbe) or bmc digital status register (0xc6). there is also an associated mask bit in register 0x35 to mask the assertion of these inputs from the alert output. reset i/o the adt7462 includes an active low reset pin (pin 14). the reset pin can be both a reset input and output. reset monitors the v cc input to the adt7462. at power-up, reset is asserted (pulled low) until 180 ms after the power supply has risen above the supply threshold. a power-on reset initializes all registers to the default values. 1v 180ms 05569-075 v cc reset figure 86. operation of reset output on power-up the reset pin can also function as a reset input. pulling this pin low externally resets the adt7462. the user should wait at least 180 ms after power-up before doing a hardware reset. the reset pulse width should be greater than 0.8 ms to ensure that a reset is registered. a hardware reset differs from a power-on reset in that not all of the registers are reinitialized to the default values. for example, limit registers are not all restored to the default values. this can be useful if the user needs to reset the part but does not want to completely reprogram the device. the register map section shows which registers are reset. locked registers are not restored to default values by a hardware reset. note that if two adt7462 devices are used in one system, the reset pins should not be connected together between devices. doing so causes one device to reset the other on a power-on reset. software reset the adt7462 can be reset in software by setting bit 7 of configuration register 0 (0x00). the code 0x6d must be written to register 0x7b before setting the software reset bit. this register is cleared to the power-on default after the software reset. note that not all registers are restored to their default values on a reset. the same registers are reset by a hardware and software reset. the register map section provides a complete reference of registers that are reset. chassis intrusion input the chassis intrusion (ci) input is an active high input intended for detection and signaling of unauthorized tampering with the system. when this input goes high, the event is latched in bit 7 of host digital status register (0xbe), and an interrupt is gener- ated. the bit remains set until cleared by writing a 1 to ci reset (ci_r), bit 5 of configuration register 3 (0x03). the ci reset bit is cleared by writing a 0 to it. the ci circuit is powered from the v batt voltage channel. pin 26 must be configured to monitor v batt and a battery must be connected to monitor ci events. ci monitoring is disabled if the measured v batt value (0x93) is less than the lower voltage limit (0x75) of pin 26. the ci input detects chassis intrusion events even when the adt7462 is powered off (provided battery voltage is applied to v batt ) but does not immediately generate an interrupt. when a chassis intrusion event is detected and latched, an interrupt is generated when the system is powered on. the actual detection of chassis intrusion is performed by an external circuit that detects, for example, when the cover has been removed. a wide variety of techniques can be used for chassis detection. for example, ? a microswitch that opens or closes when the cover is removed ? a reed switch operated by a magnet affixed to the cover ? a hall-effect switch operated by a magnet affixed to the cover ? a phototransistor that detects light when the cover is removed
adt7462 rev. a | page 60 of 92 power-up sequence the power-up sequence of the adt7462 is as follows: 1. the temperature of the thermal diode connected to pin 17 and pin 18 (only dedicated thermal diode channel) is monitored immediately on power-up of the adt7462. ideally, the hottest zone should be connected to this channel so protection is provided immediately on power-up. 2. v ccp1 is also monitored immediately on power-up. v ccp1 is typically connected to a main power rail. switching on the v ccp1 rail gates the fans quiet start-up counter. 3. v batt is monitored immediately on power-up before the setup complete bit (register 0x01, bit 5) is set. the chassis intrusion circuit (ci) is powered from v batt . if the measured v batt reading is lower than the lower limit (default = 0x80), the ci circuit is turned off. 4. pwm1, pwm2, and pwm4 are not on dedicated pins. because these pins are shared with inputs, they are allowed to float high on power-up. this means that if a fan is connected to these pins, it spins at full speed on power-up. 5. pwm2 is switched off by default (because this is a dedicated pin). if no smbus communication takes place within 4.6 seconds of the v ccp rail switching on, this pwm drive is driven to full speed. if smbus communication does take place, this pin behaves as programmed. 6. no temperature or voltage (other than v ccp1 , diode 2, and v batt ) is monitored until the setup complete bit (bit 5) is set in configuration register 1 (0x01). this allows the user to program the adt7462 as required before monitoring of all channels is enabled, thereby not generating false alert s. the setup complete bit should not be set until the device is fully configured for the desired monitoring functions. the following steps describe how to set up the adt7462: 1. power up the device. 2. choose the best-suited easy configuration option for the application, changing pin functions as required. 3. program all appropriate limits for monitored inputs. program device parameters, fan control parameters, mask bits, and anything else required for the application. 4. set the setup complete bit. do not set this bit until the device is fully set up.
adt7462 rev. a | page 61 of 92 xor tree test the adt7462 includes an xor tree test mode. this mode is useful for in-circuit test equipment at board-level testing. by applying stimulus to the pins included in the xor test, it is possible to detect opens or shorts on the system board. figure 87 shows the signals exercised in the xor tree test. the xor tree test is invoked by setting bit 6 (xor) of configuration register 3 (0x03). note that the digital inputs must be selected on multifunctional pins for the xor tree test mode. pin 13 is the open-drain output of the xor tree test. pin 1 pin 26 pin 27 pin 28 pin 29 pin 31 pin 32 pin 13 pin 25 pin 2 pin 3 pin 4 pin 7 pin 8 pin 16 pin 20 pin 21 pin 22 05569-076 figure 87. xor tree test
adt7462 rev. a | page 62 of 92 register map table 34. register map addr description r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default sw reset lockable 0x00 configuration 0 r/w sw reset vid #bytes #byt es #bytes #bytes #bytes #bytes 0x20 yes yes 0x01 configuration 1 r/w rdy lock sc dfs alert res res mon 0x81 yes yes 0x02 configuration 2 r/w #fp #fp fms vrd2 vrd1 pwm res fast 0x40 yes yes 0x03 configuration 3 r/w v_core_low xor ci_r tt vid_t sda scl gpio 0x00 yes yes 0x07 tach enable r/w t8e t7e t6e t5e t4e t3e t2e t1e 0x00 yes yes 0x08 tach configuration r/w res res res res dc 4/8 dc 3/7 dc 2/6 dc 1/5 0xe0 yes yes 0x09 gpio1_bhvr r/w d4 p4 d3 p3 d2 p2 d1 p1 0x00 yes yes 0x0a gpio2_bhvr r/w d8 p8 d7 p7 d6 p6 d5 p5 0x00 yes yes 0x0b t min _cal1 r/w res res p2r2 p2r1 p1r2 p1r1 r2 r1 0x00 yes yes 0x0c t min _cal2 r/w res ctrl loop select cyr2 cyr2 cyr2 cyr1 cyr1 cyr1 0x40 yes yes 0x0d therm configuration r/w tw2 tw2 tw2 tw1 tw1 tw1 b2 b1 0x00 yes yes 0x0e conf_ therm1 r/w res res res r3 r2 r1 local t1te 0x00 yes yes 0x0f conf_ therm2 r/w res res res r3 r2 r1 local t2te 0x00 yes yes 0x10 pin config 1 r/w vid d1 d3 pin 1 pin 2 pin 3 pin 4 pin 7 0x7f yes yes 0x11 pin config 2 r/w pin 8 pin 13 pin 15 pin 19 pin 21 pin 22 pin 23 pin 23 0xce yes yes 0x12 pin config 3 r/w pin 24 pin 24 pin 25 pin 25 pin 26 pin 26 pin 27 res 0x42 yes yes 0x13 pin config 4 r/w pin 28 pin 28 pin 29 pin 29 pin 31 pin 32 res res 0xfc yes yes 0x14 easy config r/w res res res op5 op4 op3 op2 op1 0x01 yes yes 0x16 edo enable r/w cs cs cs cs cs sc edo2 edo1 0x00 yes yes 0x18 attenuators 1 en r/w pin 22 pin 21 pin 19 pin 15 pin 13 pin 8 pin 7 res 0xff yes yes 0x19 attenuators 2 en r/w res res pin 29 pin 28 res pin 25 pin 24 pin 23 0x37 yes yes 0x1a enhanced acoustics 1 r/w rr2 rr2 rr2 rr1 rr1 rr1 en2 en1 0x00 yes yes 0x1b enhanced acoustics 2 r/w rr4 rr4 rr4 rr3 rr3 rr3 en4 en3 0x00 yes yes 0x1c fan freewheel test r/w fan 8 fan 7 fan 6 fan 5 fan 4 fan 3 fan 2 fan 1 0x00 yes yes 0x1d fans present r/w f8p f7p f6 p f5p f4p f3p f2p f1p 0x00 yes yes 0x1e fan freewheel test en r/w fan 8 fan 7 fan 6 fan 5 fan 4 fan 3 fan 2 fan 1 0x00 yes yes 0x21 pwm1 config r/w bhvr bhvr bhvr inv slow spin spin spin 0x11 yes yes 0x22 pwm2 config r/w bhvr bhvr bhvr inv slow spin spin spin 0x31 yes yes 0x23 pwm3 config r/w bhvr bhvr bhvr inv slow spin spin spin 0x51 yes yes 0x24 pwm4 config r/w bhvr bhvr bhvr inv slow spin spin spin 0x71 yes yes 0x25 pwm1, pwm2 freq r/w f2 f2 f2 f1 f1 f1 min 2 min 1 0x90 yes yes 0x26 pwm3, pwm4 freq r/w f4 f4 f4 f3 f3 f3 min 4 min 3 0x90 yes yes 0x28 pwm1 min r/w 7 6 5 4 3 2 1 0 0x80 yes yes 0x29 pwm2 min r/w 7 6 5 4 3 2 1 0 0x80 yes yes 0x2a pwm3 min r/w 7 6 5 4 3 2 1 0 0x80 yes yes 0x2b pwm4 min r/w 7 6 5 4 3 2 1 0 0x80 yes yes 0x2c pwm1 to pwm4 max r/w 7 6 5 4 3 2 1 0 0xc0 yes yes 0x30 thermal mask 1 r/w r3d r2d r1d r3 r2 r1 local res 0x00 yes no 0x31 thermal mask 2 r/w vrd2 vrd1 t2 s t2a t2% t1s t1a t1% 0xc0 yes no 0x32 voltage mask 1 r/w p23 +5v p19 p 15 +3.3v +12v3 +12v2 +12v1 0x00 yes no 0x33 voltage mask 2 r/w +1.5v1 (ich) +1.5v2 (3gio) p26 p25 p24 res res res 0x00 yes no 0x34 fan mask r/w fan 8 fan 7 fan 6 fan 5 fan 4 fan 3 fan 2 fan 1 0x00 yes no 0x35 digital mask r/w ci vid scsi2 scsi1 fan2max res res res 0x38 yes no 0x36 gpio mask r/w gpio8 gpio7 gpio6 gpio5 gpio4 gpio 3 gpio2 gpio1 0x00 yes no 0x37 edo mask 1 r/w volt temp fan re s gpio4 gpio3 gpio2 gpio1 0x00 yes no 0x38 edo mask 2 r/w volt temp fan re s gpio4 gpio3 gpio2 gpio1 0x00 yes no
adt7462 rev. a | page 63 of 92 addr description r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default sw reset lockable 0x3d device id r 7 6 5 4 3 2 1 0 0x62 no n/a 0x3e company id r 7 6 5 4 3 2 1 0 0x41 no n/a 0x3f revision number r 7 6 5 4 3 2 1 0 0x04 no n/a 0x44 local low temp limit r/w 7 6 5 4 3 2 1 0 0x40 no no 0x45 remote 1/pin 15 low temp limit r/w 7 6 5 4 3 2 1 0 0x40 no no 0x46 remote 2 low temp limit r/w 7 6 5 4 3 2 1 0 0x40 no no 0x47 remote 3/pin 19 low temp limit r/w 7 6 5 4 3 2 1 0 0x40 no no 0x48 local high limit r/w 7 6 5 4 3 2 1 0 0x95 no no 0x49 remote 1/ pin 15 high limit r/w 7 6 5 4 3 2 1 0 0x95 no no 0x4a remote 2 high limit r/w 7 6 5 4 3 2 1 0 0x95 no no 0x4b remote 3/ pin 19 high limit r/w 7 6 5 4 3 2 1 0 0x95 no no 0x4c local therm1 / +1.5v2 (3gio) high r/w 7 6 5 4 3 2 1 0 0xa4 no yes 0x4d remote 1 therm1 limit r/w 7 6 5 4 3 2 1 0 0xa4 no yes 0x4e remote 2 therm1 limit r/w 7 6 5 4 3 2 1 0 0xa4 no yes 0x4f remote 3 therm1 limit r/w 7 6 5 4 3 2 1 0 0xa4 no yes 0x50 local therm2 / +1.5v1 (ich) high r/w 7 6 5 4 3 2 1 0 0xa4 no yes 0x51 remote 1 therm2 limit r/w 7 6 5 4 3 2 1 0 0xa4 no yes 0x52 remote 2 therm2 limit r/w 7 6 5 4 3 2 1 0 0xa4 no yes 0x53 remote 3 therm2 limit r/w 7 6 5 4 3 2 1 0 0xa4 no yes 0x54 local/remote1 temp hyst r/w lh lh lh lh r1h r1h r1h r1h 0x44 no yes 0x55 remote 2/remote 3 temp hyst r/w r2h r2h r2h r2h r3h r3h r3h r3h 0x44 no yes 0x56 local offset r/w 7 6 5 4 3 2 1 0 0x00 no yes 0x57 remote 1 offset r/w 7 6 5 4 3 2 1 0 0x00 no yes 0x58 remote 2 offset r/w 7 6 5 4 3 2 1 0 0x00 no yes 0x59 remote 3 offset r/w 7 6 5 4 3 2 1 0 0x00 no yes 0x5a remote 1 operating point r/w 7 6 5 4 3 2 1 0 0xa4 yes yes 0x5b remote 2 operating point r/w 7 6 5 4 3 2 1 0 0xa4 yes yes 0x5c local temp t min r/w 7 6 5 4 3 2 1 0 0x9a yes yes 0x5d remote 1 temp t min r/w 7 6 5 4 3 2 1 0 0x9a yes yes 0x5e remote 2 temp t min r/w 7 6 5 4 3 2 1 0 0x9a yes yes 0x5f remote 3 temp t min r/w 7 6 5 4 3 2 1 0 0x9a yes yes 0x60 local t range /hyst r/w range range range range hys hys hys hys 0xc4 yes yes 0x61 remote 1 t range /hyst r/w range range range range hys hys hys hys 0xc4 yes yes 0x62 remote 2 t range /hyst r/w range range range range hys hys hys hys 0xc4 yes yes 0x63 remote 3 t range /hyst r/w range range range range hys hys hys hys 0xc4 yes yes 0x64 operating point hyst r/w hys hys hys hys res res res res 0x40 yes yes 0x68 +3.3v high limit r/w 7 6 5 4 3 2 1 0 0xff no no 0x69 pin 23 voltage high limit r/w 7 6 5 4 3 2 1 0 0xff no no
adt7462 rev. a | page 64 of 92 addr description r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default sw reset lockable 0x6a pin 24 voltage high limit r/w 7 6 5 4 3 2 1 0 0xff no no 0x6b pin 25 voltage high limit r/w 7 6 5 4 3 2 1 0 0xff no no 0x6c pin 26 voltage high limit r/w 7 6 5 4 3 2 1 0 0xff no no 0x6d +12v1 low limit r/w 7 6 5 4 3 2 1 0 0x00 no no 0x6e +12v2 low limit r/w 7 6 5 4 3 2 1 0 0x00 no no 0x6f +12v3 low limit r/w 7 6 5 4 3 2 1 0 0x00 no no 0x70 +3.3v low limit r/w 7 6 5 4 3 2 1 0 0x00 no no 0x71 +5v low limit r/w 7 6 5 4 3 2 1 0 0x00 no no 0x72 pin 23 voltage low limit r/w 7 6 5 4 3 2 1 0 0x20 no no 0x73 pin 24 voltage low limit r/w 7 6 5 4 3 2 1 0 0x00 no no 0x74 pin 25 voltage low limit r/w 7 6 5 4 3 2 1 0 0x00 no no 0x75 pin 26 voltage low limit r/w 7 6 5 4 3 2 1 0 0x80 no no 0x76 +1.5v1 (ich) low limit r/w 7 6 5 4 3 2 1 0 0x00 no no 0x77 +1.5v2 (3gio) low limit r/w 7 6 5 4 3 2 1 0 0x00 no no 0x78 tach1 limit/vid r/w 7 6 5 4 3 2 1 0 0xff no yes 0x79 tach2 limit r/w 7 6 5 4 3 2 1 0 0xff no yes 0x7a tach3 limit r/w 7 6 5 4 3 2 1 0 0xff no yes 0x7b tach4 limit r/w 7 6 5 4 3 2 1 0 0xff no yes 0x7c tach5/+12v1 high limit r/w 7 6 5 4 3 2 1 0 0xff no yes 0x7d tach6/+12v2 high limit r/w 7 6 5 4 3 2 1 0 0xff no yes 0x7e tach7/+5v high limit r/w 7 6 5 4 3 2 1 0 0xff no yes 0x7f tach8/+12v3 high limit r/w 7 6 5 4 3 2 1 0 0xff no yes 0x80 therm1 timer limit r/w 7 6 5 4 3 2 1 0 0xff no yes 0x81 therm2 timer limit r/w 7 6 5 4 3 2 1 0 0xff no yes 0x88 local temp value, lsbs r 7 6 5 4 3 2 1 0 0x00 no no 0x89 local temp value, msbs r 7 6 5 4 3 2 1 0 0x00 no no 0x8a remote 1 temp, lsbs r 7 6 5 4 3 2 1 0 0x00 no no 0x8b remote 1 temp, msbs, pin 15 voltage r 7 6 5 4 3 2 1 0 0x00 no no 0x8c remote 2 temp, lsbs r 7 6 5 4 3 2 1 0 0x00 no no 0x8d remote 2 temp, msbs r 7 6 5 4 3 2 1 0 0x00 no no 0x8e remote 3 temp, lsbs r 7 6 5 4 3 2 1 0 0x00 no no 0x8f remote 3 temp, msbs, pin 19 voltage r 7 6 5 4 3 2 1 0 0x00 no no 0x90 pin 23 voltage r 7 6 5 4 3 2 1 0 0x00 no no 0x91 pin 24 voltage r 7 6 5 4 3 2 1 0 0x00 no no 0x92 pin 25 voltage r 7 6 5 4 3 2 1 0 0x00 no no 0x93 pin 26 voltage r 7 6 5 4 3 2 1 0 0x00 no no 0x94 +1.5v1 (ich) voltage r 7 6 5 4 3 2 1 0 0x00 no no 0x95 +1.5v2 (3gio) voltage r 7 6 5 4 3 2 1 0 0x00 no no
adt7462 rev. a | page 65 of 92 addr description r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default sw reset lockable 0x96 +3.3v voltage r 7 6 5 4 3 2 1 0 0x00 no no 0x97 vid value r 7 6 5 4 3 2 1 0 0x00 no no 0x98 tach1 value, lsbs r 7 6 5 4 3 2 1 0 0xff no no 0x99 tach1 value, msbs r 7 6 5 4 3 2 1 0 0xff no no 0x9a tach2 value, lsbs r 7 6 5 4 3 2 1 0 0xff no no 0x9b tach2 value, msbs r 7 6 5 4 3 2 1 0 0xff no no 0x9c tach3 value, lsbs r 7 6 5 4 3 2 1 0 0xff no no 0x9d tach3 value, msbs r 7 6 5 4 3 2 1 0 0xff no no 0x9e tach4 value, lsbs r 7 6 5 4 3 2 1 0 0xff no no 0x9f tach4 value, msbs r 7 6 5 4 3 2 1 0 0xff no no 0xa0 unused r 7 6 5 4 3 2 1 0 n/a no no 0xa1 unused r 7 6 5 4 3 2 1 0 n/a no no 0xa2 tach5 value, lsb r 7 6 5 4 3 2 1 0 0xff no no 0xa3 tach5 msb/ +12v1 voltage r 7 6 5 4 3 2 1 0 0xff no no 0xa4 tach6 value, lsb r 7 6 5 4 3 2 1 0 0xff no no 0xa5 tach6 msb/+12v2 voltage r 7 6 5 4 3 2 1 0 0xff no no 0xa6 tach7 value, lsb r 7 6 5 4 3 2 1 0 0xff no no 0xa7 tach7 msb/+5v voltage r 7 6 5 4 3 2 1 0 0xff no no 0xa8 tach8 value, lsb r 7 6 5 4 3 2 1 0 0xff no no 0xa9 tach8 msb/+12v3 voltage r 7 6 5 4 3 2 1 0 0xff no no 0xaa pwm1 duty cycle r/w 7 6 5 4 3 2 1 0 0x00 no no 0xab pwm2 duty cycle r/w 7 6 5 4 3 2 1 0 0x00 no no 0xac pwm3 duty cycle r/w 7 6 5 4 3 2 1 0 0x00 no no 0xad pwm4 duty cycle r/w 7 6 5 4 3 2 1 0 0x00 no no 0xae therm1 % on-time r 7 6 5 4 3 2 1 0 0x00 no no 0xaf therm2 % on-time r 7 6 5 4 3 2 1 0 0x00 no no 0xb8 thermal status 1, host r r3d r2d r1d r3 r2 r1 local res 0x00 yes no 0xb9 thermal status 2, host r vr2 vr1 t2s t2a t2% t1s t1a t1% 0x00 yes no 0xba thermal status 3, host r r3t2 r2t2 r1t2 lt2 r3t1 r2t1 r1t1 lt1 0x00 yes no 0xbb voltage status 1, host r pin 23 +5v pin 19 pin 15 +3.3v +12v3 +12v2 +12v1 0x00 yes no 0xbc voltage status 2, host r +1.5v1 (ich) +1.5v2 (3gio) pin 26 pin 25 pin 24 res res res 0x00 yes no 0xbd fan status, host r fan 8 fan 7 fan 6 fan 5 fan 4 fan 3 fan 2 fan 1 0x00 yes no 0xbe digital status, host r ci vid scsi2 scsi1 fan2max res res res 0x00 yes no 0xbf gpio status, host r/w gpio8 gpio7 gpio 6 gpio5 gpio4 gpio3 gp io2 gpio1 0x00 yes no 0xc0 thermal status 1, bmc r r3d r2d r1d r3 r2 r1 local res 0x00 yes no 0xc1 thermal status 2, bmc r vr2 vr1 t2s t2a t2% t1s t1a t1% 0x00 yes no 0xc3 voltage status 1, bmc r pin 23 +5v pin 19 pin 15 +3.3v +12v3 +12v2 +12v1 0x00 yes no 0xc4 voltage status 2, bmc r +1.5v1 (ich) +1.5v2 (3gio) pin 26 pin 25 pin 24 res res res 0x00 yes no 0xc5 fan status, bmc r fan 8 fan 7 fan 6 fan 5 fan 4 fan 3 fan 2 fan 1 0x00 yes no 0xc6 digital status, bmc r ci vid scsi2 scsi1 fan2max res res res 0x00 yes no
adt7462 rev. a | page 66 of 92 table 35. register 0x00co nfiguration register 0 1 bit name r/w description [5:0] #bytes block read r/w these bits set the number of registers to be read in a block read. default = 0x20. 6 vid decoder r/w 0 = vr10 decoding spec; 1 = vr11 decoding spec. default = 0. 7 sw reset r/w setting this bit to 1 restores all unlocked regi sters to their default values. self-clearing. write 0x6d to register 0x7b before setting th is bit to get a software reset. default = 0. 1 por = 0x20, lock = y, sw reset = y. table 36. register 0x01co nfiguration register 1 1 bit name r/w description 0 monitor r/w setting this bit to 1 enables temperature and volt age measurements. when this bit is set to 0, temperature and voltage measurements are disabled. default = 1. 1 reserved r/w reserved. default = 0. 2 reserved r/w reserved. default = 0. 3 alert mode r/w this bit sets the alert mode in the adt7462. 1 = comparator mode, 0 = smbalert mode (default). 4 disable fast spin-up r/w setting this bit to 1 disables the fa st spin-up (for two tach pulses) for the fans. instead, the fans spin up for the programmed fan start-up timeout. default = 0. 5 setup complete r/w setting this bit to 1 tells the adt7462 that setup is complete and that monitoring of all selected channels should begin. default = 0. 6 lock write once logic 1 locks all limit values at their current settings. when this bit is set, all lockable registers become read-only and cannot be modified until the adt7462 is powered down and powered up again. this prevents rogue programs, such as viruses, from mo difying critical system limit settings. lockable. 7 rdy r this bit is set to 1 to indicate that the adt 7462 is fully powered up and ready to start monitoring. 1 por = 0x81, lock = y, sw reset = y. table 37. register 0x02co nfiguration register 2 1 bit name r/w description 0 fast r/w in low frequency, pwm fan speed measurements ar e made once a second. setting this bit to 1 increases the frequency of the fan speed meas urements to 4 times a second. default = 0. 1 reserved r/w reserved. default = 0. 2 pwm mode r/w this bit sets the pwm frequency mode. 0 = low frequency pwm; frequency programmable between 11 hz and 88.2 hz. default = 35.3 hz. 1 = high frequency mode, 22.5 khz. 3 vrd1 boost r/w setting this bit to 0 causes the fans to go to full speed on assertion of vrd1. default = 0. when this bit is set to 1, vrd1 assert ions have no effect on the fan speed. 4 vrd2 boost r/w setting this bit to 0 causes the fans to go to full speed on assertion of vrd2. default = 0. when this bit is set to 1, vrd2 assert ions have no effect on the fan speed. 5 fans full speed r/w setting this bit to 1 drives the fans to full speed. default = 0. [7:6] #tach pulses r/w in low frequency mode, the adt7462 must pulse stretc h to get an accurate fan speed measurement. the speed is always measured between the 2nd risi ng edge and one tach pulses later. this bit determines the last tach pulse. therefore, if the fa n speed is to be measured between the second and fourth tach pulse, 01 is written to these bits. x = 1 = 00 x = 2 = 01 (default) x = 3 = 10 x = 4 = 11 1 por = 0x40, lock = y, sw reset = y.
adt7462 rev. a | page 67 of 92 table 38. register 0x03co nfiguration register 3 1 bit name r/w description 0 gpio_en r/w setting this bit to 1 enables the gpios. default = 0. 1 scl_timeout r/w 1 = scl timeout enabled. 0 = scl timeout disabled = default. 2 sda_timeout r/w 1 = sda timeout enabled. 0 = sda timeout disabled = default. 3 vid_threshold r/w this bit sets the digital threshold for the vid digital inputs. 0 =default. 1 = low thresholds selected = 0.65 v. 4 therm _threshold r/w this bit sets the digital threshold for the therm digital inputs. 0 =default. 1 = low thresholds selected = 2/3 v ccp1 (pin 23). 5 ci reset r/w setting this bit to 1 resets the chassis intrusion circuit. this bit clears itself. default = 0. 6 xor tree r/w setting this bit to 1 en ables the xor tree test. default = 0. 7 v_core_low r/w setting this bit to 1 enables v_core_low. default = 0. 1 por = 0x00, lock = y, sw reset = y. table 39. register 0x07tach enable register 1 bit name r/w description 0 tach1 r/w setting this bit to 1 enable s the tach1 measurement. default = 0. 1 tach2 r/w setting this bit to 1 enable s the tach2 measurement. default = 0. 2 tach3 r/w setting this bit to 1 enable s the tach3 measurement. default = 0. 3 tach4 r/w setting this bit to 1 enable s the tach4 measurement. default = 0. 4 tach5 r/w setting this bit to 1 enable s the tach5 measurement. default = 0. 5 tach6 r/w setting this bit to 1 enable s the tach6 measurement. default = 0. 6 tach7 r/w setting this bit to 1 enable s the tach7 measurement. default = 0. 7 tach8 r/w setting this bit to 1 enable s the tach8 measurement. default = 0. 1 por = 0x00, lock = y, sw reset = y. table 40. register 0x08tach configuration register 1 bit name r/w description 0 dc 1/5 r/w setting this bit to 1 enables cont inuous measurements on tach1 and tach5 in low frequency pwm mode. continuous measurement means that pulse stretching is turned off and the pwm output and tach inputs are no longer synchronized. default = 0. 1 dc 2/6 r/w setting this bit to 1 enables cont inuous measurements on tach2 and tach6 in low frequency pwm mode. continuous measurement means that pulse stretching is turned off and the pwm output and tach inputs are no longer synchronized. default = 0. 2 dc 3/7 r/w setting this bit to 1 enables cont inuous measurements on tach3 and tach7 in low frequency pwm mode. continuous measurement means that pulse stretching is turned off and the pwm output and tach inputs are no longer synchronized. default = 0. 3 dc 4/8 r/w setting this bit to 1 enables cont inuous measurements on tach4 and tach8 in low frequency pwm mode. continuous measurement means that pulse stretching is turned off and the pwm output and tach inputs are no longer synchronized. default = 0. [7:4] reserved r reserved for future use. 1 por = 0xe0, lock = y, sw reset = y.
adt7462 rev. a | page 68 of 92 table 41. register 0x09gpio configuration register 1 1 bit name r/w description 0 gpio1_p r/w this bit sets the polarity of gpio 1. 0 = default = active low. 1= active high. 1 gpio1_d r/w this bit sets the direction of gpio1. 0 = default = input. 1= output. 2 gpio2_p r/w this bit sets the polarity of gpio 2. 0 = default = active low. 1= active high. 3 gpio2_d r/w this bit sets the direction of gpio2. 0 = default = input. 1= output. 4 gpio3_p r/w this bit sets the polarity of gpio 3. 0 = default = active low. 1= active high. 5 gpio3_d r/w this bit sets the direction of gpio3. 0 = default = input. 1= output. 6 gpio4_p r/w this bit sets the polarity of gpio 4. 0 = default = active low. 1= active high. 7 gpio4_d r/w this bit sets the direction of gpio4. 0 = default = input. 1= output. 1 por = 0x00, lock = y, sw reset = y. table 42. register 0x0agpio configuration register 2 1 bit name r/w description 0 gpio5_p r/w this bit sets the polarity of gpio 5. 0 = default = active low. 1= active high. 1 gpio5_d r/w this bits sets the direction of gpio5. 0 = default = input. 1= output. 2 gpio6_p r/w this bit sets the polarity of gpio 6. 0 = default = active low. 1= active high. 3 gpio6_d r/w this bits sets the direction of gpio6. 0 = default = input. 1= output. 4 gpio7_p r/w this bit sets the polarity of gpio 7. 0 = default = active low. 1= active high. 5 gpio7_d r/w this bits sets the direction of gpio7. 0 = default = input. 1= output. 6 gpio8_p r/w this bit sets the polarity of gpio 8. 0 = default = active low. 1= active high. 7 gpio8_d r/w this bits sets the direction of gpio8. 0 = default = input. 1= output. 1 por = 0x00, lock = y, sw reset = y. table 43. register 0x0bdynamic t min control register 1 1 bit name r/w description 0 remote 1 en r/w setting this bit to 1 enables dynamic t min control for the remote 1 channel. default = 0. 1 remote 2 en r/w setting this bit to 1 enables dynamic t min control for the remote 2 channel. default = 0. 2 p1r1 r/w p1r1 = 1 copies the remote 1 current temperature to the remote 1 operating point register if therm1 is asserted externally. this happens only if the current temperature is less than the value in the operating point register. the operating point contains the temperature at which therm1 is asserted. p1r1 = 0 (default) ignores any therm1 assertions on the therm1 pin. the remote 1 operating point register reflects its programmed value. 3 p1r2 r/w p1r2 = 1 copies the remote 2 current temperature to the remote 2 operating point register if therm1 is asserted externally. this happens only if the current temperature is less than the value in the operating point register. the operating point contains the temperature at which therm1 is asserted. p1r2 = 0 (default) ignores any therm1 assertions on the therm1 pin. the remote 2 operating point register reflects its programmed value. 4 p2r1 r/w p2r1 = 1 copies the remote 1 current temperature to the remote 1 operating point register if therm2 is asserted externally. this happens only if the current temperature is less than the value in the operating point register. the operating point contains the temperature at which therm2 is asserted. p2r1 = 0 (default) ignores any therm2 assertions on the therm2 pin. the remote 1 operating point register reflects its programmed value. 5 p2r2 r/w p2r2 = 1 copies the remote 2 current temperature to the remote 2 operating point register if therm2 is asserted externally. this happens only if the current temperature is less than the value in the operating point register. the operating point contains the temperature at which therm2 is asserted. p2r2 = 0 (default) ignores any therm2 assertions on the therm2 pin. the remote 2 operating point register reflects its programmed value. [7:6] reserved r/w reserved for future use. 1 por = 0x00, lock = y, sw reset = y.
adt7462 rev. a | page 69 of 92 table 44. register 0x0cdynamic t min control register 2 1 bit name r/w description [2:0] cyr1 r/w three-bit remote 1 cycle value. these three bits de fine the delay time between making subsequent t min adjustments in the control loop for the remote 1 temperature channel, in terms of number of monitoring cycles. the system has associated thermal time cons tants that must be found to optimize the response of fans and the control loop. bits decrease cycle increase cycle 000 8 cycles (1 sec) 16 cycles (2 sec) 001 16 cycles (2 sec) 32 cycles (4 sec) 010 32 cycles (4 sec) 64 cycles (8 sec) 011 64 cycles (8 sec) 128 cycles (16 sec) 100 128 cycles (16 sec) 256 cycles (32 sec) 101 256 cycles (32 sec) 512 cycles (64 sec) 110 512 cycles (64 sec) 1024 cycles (128 sec) 111 1024 cycles (128 sec) 2048 cycles (256 sec) [5:3] cyr2 r/w three-bit remote 2 cycle value. these three bits de fine the delay time between making subsequent t min adjustments in the control loop for the remote 2 temperature channel, in terms of number of monitoring cycles. the system has associated thermal time cons tants that must be found to optimize the response of fans and the control loop. bits decrease cycle increase cycle 000 8 cycles (1 sec) 16 cycles (2 sec) 001 16 cycles (2 sec) 32 cycles (4 sec) 010 32 cycles (4 sec) 64 cycles (8 sec) 011 64 cycles (8 sec) 128 cycles (32 sec) 100 128 cycles (16 sec) 256 cycles (32 sec) 101 256 cycles (32 sec) 1024 cycles (64 sec) 110 512 cycles (64 sec) 1024 cycles (128 sec) 111 1024 cycles (128 sec) 2048 cycles (256 sec) 6 control loop select r/w this bit allows the user to select between two control loops. 0 makes the control loop backwards compatible with the adt7463 and adt7468 . 1 = adt7462 control loop (default). 7 reserved r reserved for future use. 1 por = 0x40, lock = y, sw reset = y.
adt7462 rev. a | page 70 of 92 table 45. register 0x0d therm configuration register 1 bit name r/w description 0 boost 1 r/w setting this bit to 0 causes the fans to go to maximum pwm on assertion of therm1 as an output. setting this bit to 1 means that th e fan speed is not affected when the therm1 temperature limit is exceeded. default = 0. 1 boost 2 r/w setting this bit to 0 causes the fans to go to maximum pwm on assertion of therm2 as an output. setting this bit to 1 means that th e fan speed is not affected when the therm2 temperature limit is exceeded. default = 0. [4:2] therm1 timer window r/w these bits set the timer window for measuring therm1 assertions. 000 = 0.25 sec 001 = 0.5 sec 010 = 1 sec 011 = 2 sec 100 = 4 sec 101 = 8 sec 110 = 8 sec 111 = 8 sec [7:5] therm2 timer window r/w these bits set the timer window for measuring therm2 assertions. 000 = 0.25 sec 001 = 0.5 sec 010 = 1 sec 011 = 2 sec 100 = 4 sec 101 = 8 sec 110 = 8 sec 111 = 8 sec 1 por = 0x00, lock = y, sw reset = y. table 46. register 0x0e therm1 configuration register 1 bit name r/w description 0 therm1 timer enable r/w enables the therm1 timer circuit. default = 0. 1 therm1 _local r/w setting the bit to 1 means that the therm1 pin is asserted low as an output whenever the local temperature exceeds the local therm1 temperature limit. default = 0. 2 therm1 _remote 1 r/w setting the bit to 1 means that the therm1 pin is asserted low as an output whenever the remote 1 temperature exceeds the remote 1 therm1 temperature limit. default = 0. 3 therm1 _remote 2 r/w setting the bit to 1 means that the therm1 pin is asserted low as an output whenever the remote 2 temperature exceeds the remote 2 therm1 temperature limit. default = 0. 4 therm1 _remote 3 r/w setting the bit to 1 means that the therm1 pin is asserted low as an output whenever the remote 3 temperature exceeds the remote 3 therm1 temperature limit. default = 0. [7:5] reserved r reserved for future use. 1 por = 0x00, lock = y, sw reset = y.
adt7462 rev. a | page 71 of 92 table 47. register 0x0f therm2 configuration register 1 bit name r/w description 0 therm2 timer enable r/w enables the therm2 timer circuit. default = 0. 1 therm2 _local r/w setting the bit to 1 means that the therm2 pin is asserted low as an output whenever the local temperature exceeds the local therm2 temperature limit. default = 0. 2 therm2 _remote 1 r/w setting the bit to 1 means that the therm2 pin is asserted low as an output whenever the remote 1 temperature exceeds the remote 1 therm2 temperature limit. default = 0. 3 therm2 _remote 2 r/w setting the bit to 1 means that the therm2 pin is asserted low as an output whenever the remote 2 temperature exceeds the remote 2 therm2 temperature limit. default = 0. 4 therm2 _remote 3 r/w setting the bit to 1 means that the therm2 pin is asserted low as an output whenever the remote 3 temperature exceeds the remote 3 therm2 temperature limit. default = 0. [7:5] reserved r reserved for future use. 1 por = 0x00, lock = y, sw reset = y. table 48. register 0x10pin configuration register 1 1 bit name r/w description 0 pin 7 r/w 0 = +12v1; 1 = tach5 input. default =1. 1 pin 4 r/w 0 = gpio4; 1= tach4 input (that is, if the vids are not selected). default = 1. 2 pin 3 r/w 0 = gpio3; 1= tach3 input (that is, if the vids are not selected). default = 1. 3 pin 2 r/w 0 = gpio2; 1= tach2 input (that is, if the vids are not selected). default = 1. 4 pin 1 r/w 0 = gpio1; 1= tach1 input (that is, if the vids are not selected). default = 1. 5 diode 3 r/w 1 enables the d3+ and d3? inputs on pin 19 and pin 20. 0 enables the voltage measurement input and scsi_term2 input. default = 1. 6 diode 1 r/w 1 enables the d1+ and d1? inputs on pin 15 and pin 16. 0 enables the voltage measurement input and scsi_term1 input. default = 1. 7 vids r/w setting this bit to 1 enab les the vids on pin 1 to pin 4, pin 28, pin 31, and pin 32. default = 0. 1 por = 0x7f, lock = y, sw reset = y. table 49. register 0x11pin configuration register 2 1 bit name r/w description [1:0] pin 23 r/w 00 = v ccp1 selected. 01 = +2.5v. 10 = +1.8v (default). 11 = +1.5v. 2 pin 22 r/w 0 = +12v3; 1 = tach8. default = 1. 3 pin 21 r/w 0 = +5v; 1 = tach7. default = 1. 4 pin 19 r/w 0 = +1.25v; 1 = +0.9v (that is, if rt3 is not selected). default = 0. 5 pin 15 r/w 0 = +2.5v, 1 = +1.8v (that is, if rt1 is not selected). default = 0. 6 pin 13 r/w 0 = +3.3v; 1 = pwm4. default = 1. 7 pin 8 r/w 0 = +12v2; 1 = tach6. default = 1. 1 por = 0xce, lock = y, sw reset = y.
adt7462 rev. a | page 72 of 92 table 50. register 0x12pin configuration register 3 1 bit name r/w description 0 reserved r reserved for future use. 1 pin 27 r/w 0 = fan2max ; 1 = chassis intrusion (default). [3:2] pin 26 r/w 00 = v batt selected (default). 01 = +1.2v2 (fsb_v tt ). 10 = vr_hot2. 11 = vr_hot2. [5:4] pin 25 r/w 00 = +3.3v selected (default). 01 = +1.2v1 (g bit ). 10 = vr_hot1. 11 = vr_hot1. [7:6] pin 24 r/w 00 = v ccp2 selected. 01 = +2.5v (default). 10 = +1.8v. 11 = +1.5v. 1 por = 0x42, lock = y, sw reset = y. table 51. register 0x13pin configuration register 4 1 bit name r/w description [1:0] reserved r reserved. 2 pin 32 r/w 0 = gpio6; 1 = pwm2 (pin 32 is vid5 if vids are selected). default = 1. 3 pin 31 r/w 0 = gpio5; 1 = pwm1 (pin 31 is vid4 if vids are selected). default = 1. [5:4] pin 29 (pin 28, +1.5v monitoring 2 ) r/w 00 = gpio8. 01 = +1.5v (measured on pin 28). 10 = therm2 . 11 = therm2 (default). (pin 28 is vid6 if vids are selected.) [7:6] pin 28 (pin 29, +1.5v monitoring 2 ) r/w 00 = gpio7. 01 = +1.5v (measured on pin 29). 10 = therm1 . 11 = therm1 (default). 1 por = 0xfc, lock = y, sw reset = y. 2 +1.5v can be monitored on pin 28 and pin 29 only when both are co nfigured as +1.5v inputs. this means that +1.5v is measured o n both pins or on neither. +1.5v monitoring cannot be combin ed with another function on the other pin. for example, if pin 29 is configured as +1.5v, then therm1 cannot be selected on pin 28, because they share the same selection bits. table 52. register 0x14easy configuration options 1 bit name r/w description 0 easy option 1 select r/w setting this bit to 1 enables easy option 1. 1 easy option 2 select r/w setting th is bit to 1 enables easy option 2. 2 easy option 3 select r/w setting th is bit to 1 enables easy option 3. 3 easy option 4 select r/w setting this bit to 1 enables easy option 4. 4 easy option 5 select r/w setting this bit to 1 enables easy option 5. [7:5] reserved r reserved for future use. 1 por = 0x01, lock = y, sw reset = y.
adt7462 rev. a | page 73 of 92 table 53. register 0x16ed o/single-channel enable 1 bit name r/w description 0 edo_en1 r/w enable edo on gpio5. default = 0. 1 edo_en2 r/w enable edo on gpio6. default = 0. 2 single-channel mode select r/w setting this bit to 1 places the adt7462 in single -channel mode. this means that it converts on one channel only. the channel it converts on is set using the channel select bits in this register. default = 0. [7:3] channel select r/w these bits are used to set the sing le channel that the adt7462 measures in single-channel mode. 0000 0 = pin 26 (default) 0000 1 = remote 1 temperature 0001 0 = remote 2 temperature 0001 1 = remote 3 temperature 0010 0 = local temperature 0010 1 = +12v1 0011 0 = +12v2 0011 1 = +12v3 0100 0 = +3.3v 0100 1 = pin 15 voltage 0101 0 = pin 19 voltage 0101 1 = +5v 0110 0 = pin 23 voltage 0110 1 = pin 24 voltage 0111 0 = pin 25 voltage 1000 0 = +1.5v1 (ich) voltage 1000 1 = +1.5v2 (3gio) voltage 1 por = 0x00, lock = y, sw reset = y. table 54. register 0x18voltage attenuator configuration 1 1 bit name r/w description 0 reserved r reserved for future use. 1 attenuator pin 7 r/w setting this bit to 0 removes the attenuators for pin 7. default = 1 = attenuators enabled. 2 attenuator pin 8 r/w setting this bit to 0 removes the attenuators for pin 8. default = 1 = attenuators enabled. 3 attenuator pin 13 r/w setting this bit to 0 removes the attenuators for pin13. default = 1 = attenuators enabled. 4 attenuator pin 15 r/w setting this bit to 0 removes the attenuators for pin 15. default = 1 = attenuators enabled. 5 attenuator pin 19 r/w setting this bit to 0 removes the attenuators for pin 19. default = 1 = attenuators enabled. 6 attenuator pin 21 r/w setting this bit to 0 removes the attenuators for pin 21. default = 1 = attenuators enabled. 7 attenuator pin 22 r/w setting this bit to 0 removes the attenuators for pin 22. default = 1 = attenuators enabled. 1 por = 0xff, lock = y, sw reset = y. table 55. register 0x19voltage attenuator configuration 2 1 bit name r/w description 0 attenuator pin 23 r/w setting this bit to 0 removes the attenuators for pin 23. default = 1 = attenuators enabled. 1 attenuator pin 24 r/w setting this bit to 0 removes the attenuators for pin 24. default = 1 = attenuators enabled. 2 attenuator pin 25 r/w setting this bit to 0 removes the attenuators for pin 25. default = 1 = attenuators enabled. 3 reserved r/w reserved for future use. default = 0. 4 attenuator pin 28 r/w setting this bit to 0 removes the attenuators for pin 28. default = 1 = attenuators enabled. 5 attenuator pin 29 r/w setting this bit to 0 removes the attenuators for pin 29. default = 1 = attenuators enabled. [7:6] reserved r/w reserved for future use. default = 00. 1 por = 0x37, lock = y, sw reset = y.
adt7462 rev. a | page 74 of 92 table 56. register 0x1aenhanced acoustics register 1 1 bit name r/w description 0 en1 r/w setting this bit to 1 enables the enhanced acoustics mode for pwm1; 0 disables it. default = 0. 1 en2 r/w setting this bit to 1 enables the enhanced acoustics mode for pwm2; 0 disables it. default = 0. [4:2] ramp rate 1 r/w these bits set the ramp rate fo r the enhanced acoustics mode for pwm1. default = 000. time slot increase time for 33% to 100% 000 = 1 35 sec 001 = 2 17.6 sec 010 = 3 11.8 sec 011 = 5 7 sec 100 = 8 4.4 sec 101 = 12 3 sec 110 = 24 1.6 sec 111 = 48 0.8 sec [7:5] ramp rate 2 r/w these bits set the ramp rate fo r the enhanced acoustics mode for pwm2. default = 000. time slot increase time for 33% to 100% 000 = 1 35 sec 001 = 2 17.6 sec 010 = 3 11.8 sec 011 = 5 7 sec 100 = 8 4.4 sec 101 = 12 3 sec 110 = 24 1.6 sec 111 = 48 0.8 sec 1 por = 0x00, lock = y, sw reset = y. table 57. register 0x1benhanced acoustics register 2 1 bit name r/w description 0 en3 r/w setting this bit to 1 enables the enhanced acoustics mode for pwm3; 0 disables it. default = 0. 1 en4 r/w setting this bit to 1 enables the enhanced acoustics mode for pwm4; 0 disables it. default = 0. [4:2] ramp rate 3 r/w these bits set the ramp rate fo r the enhanced acoustics mode for pwm3. default = 000. time slot increase time for 33% to 100% 000 = 1 35 sec 001 = 2 17.6 sec 010 = 3 11.8 sec 011 = 5 7 sec 100 = 8 4.4 sec 101 = 12 3 sec 110 = 24 1.6 sec 111 = 48 0.8 sec [7:5] ramp rate 4 r/w these bits set the ramp rate fo r the enhanced acoustics mode for pwm4. default = 000. time slot increase time for 33% to 100% 000 = 1 35 sec 001 = 2 17.6 sec 010 = 3 11.8 sec 011 = 5 7 sec 100 = 8 4.4 sec 101 = 12 3 sec 110 = 24 1.6 sec 111 = 48 0.8 sec 1 por = 0x00, lock = y, sw reset = y.
adt7462 rev. a | page 75 of 92 table 58. register 0x1cfan freewheeling test 1 bit name r/w description 0 test fan 1 r/w fan freewheeling test bit for fan 1. this bit self-clears when the test is complete. 1 test fan 2 r/w fan freewheeling test bit for fan 2. this bit self-clears when the test is complete. 2 test fan 3 r/w fan freewheeling test bit for fan 3. this bit self-clears when the test is complete. 3 test fan 4 r/w fan freewheeling test bit for fan 4. this bit self-clears when the test is complete. 4 test fan 5 r/w fan freewheeling test bit for fan 5. this bit self-clears when the test is complete. 5 test fan 6 r/w fan freewheeling test bit for fan 6. this bit self-clears when the test is complete. 6 test fan 7 r/w fan freewheeling test bit for fan 7. this bit self-clears when the test is complete. 7 test fan 8 r/w fan freewheeling test bit for fan 8. this bit self-clears when the test is complete. 1 por = 0x00, lock = y, sw reset = y. table 59. register 0x1dfans present 1 bit name r/w description 0 fan 1 present r/w set this bit to 1 when fan 1 is present. 1 fan 2 present r/w set this bit to 1 when fan 2 is present. 2 fan 3 present r/w set this bit to 1 when fan 3 is present. 3 fan 4 present r/w set this bit to 1 when fan 4 is present. 4 fan 5 present r/w set this bit to 1 when fan 5 is present. 5 fan 6 present r/w set this bit to 1 when fan 6 is present. 6 fan 7 present r/w set this bit to 1 when fan 7 is present. 7 fan 8 present r/w set this bit to 1 when fan 8 is present. 1 por = 0x00, lock = y, sw reset = y. table 60. register 0x1efan freewheeling test enable 1 bit name r/w description 0 test fan 1 r/w setting this bit to 1 enables the fan freewheeling test for fan 1. 1 test fan 2 r/w setting this bit to 1 enables the fan freewheeling test for fan 2. 2 test fan 3 r/w setting this bit to 1 enables the fan freewheeling test for fan 3. 3 test fan 4 r/w setting this bit to 1 enables the fan freewheeling test for fan 4. 4 test fan 5 r/w setting this bit to 1 enables the fan freewheeling test for fan 5. 5 test fan 6 r/w setting this bit to 1 enables the fan freewheeling test for fan 6. 6 test fan 7 r/w setting this bit to 1 enables the fan freewheeling test for fan 7. 7 test fan 8 r/w setting this bit to 1 enables the fan freewheeling test for fan 8. 1 por = 0x00, lock = y, sw reset = y.
adt7462 rev. a | page 76 of 92 table 61. pwm configuration registers 1 register address r/w description power on default 0x21 r/w pwm1 configuration register 0x11 0x22 r/w pwm2 configuration register 0x31 0x23 r/w pwm3 configuration register 0x51 0x24 r/w pwm4 configuration register 0x71 1 lock = y, sw reset = y. table 62. register 0x21, register 0x22, register 0x23, regi ster 0x24pwm1, pwm2, pwm3, and pwm4 configuration registers bit name r/w description [2:0] spin-up timeout r/w these bits set the duration of the fan start-up timeout and the timeout for the fan freewheeling test. 000 = no start-up timeout 001 = 100 ms 010 = 250 ms 011 = 400 ms 100 = 667 ms 101 = 1 sec 110 = 2 sec 111 = 32 sec 3 slow r/w setting this bit to 1 makes the ramp rate of the enhance acoustics mode four times longer. 4 inv r/w setting this bit to 0, the pwm outputs are active high. setting this bit to 1, the pwm outputs are active low (default). [7:5] bhvr r/w these bits determine which temperature channel controls the fans in the automatic fan speed control loop. 000 = local temperature 001 = remote 1 temperature 010 = remote 2 temperature 011 = remote 3 temperature 100 = off 101 = maximum fan speed calculated by the local and remote 3 temperature channels 110 = maximum fan speed calculated by all four channels 111 = manual mode
adt7462 rev. a | page 77 of 92 table 63. register 0x25pwm1, pwm2 frequency 1 bit name r/w description 0 min 1 r/w when the adt7462 is in automatic fan control mode, this bit defines whether pwm1 is off (0% duty cycle) or at minimum pwm1 duty cycle when the controlling temperature is below its t min ? hysteresis value. 0 = 0% duty cycle below t min ? hysteresis (default); 1 = minimum pwm1 duty cycle below t min ? hysteresis. 1 min 2 r/w when the adt7462 is in automatic fan control mode, this bit defines whether pwm2 is off (0% duty cycle) or at minimum pwm2 duty cycle when the controlling temperature is below its t min ? hysteresis value. 0 = 0% duty cycle below t min ? hysteresis (default); 1 = minimum pwm2 duty cycle below t min ? hysteresis. [4:2] low freq 1 r/w these bits set the frequency of pwm1 when configured in low frequency mode. 000 = 11 hz 001 = 14.7 hz 010 = 22.1 hz 011 = 29.4 hz 100 = 35.3 hz (default) 101 = 44.1 hz 110 = 58.8 hz 111 = 88.2 hz [7:5] low freq 2 r/w these bits set the frequency of pwm2 when configured in low frequency mode. 000 = 11 hz 001 = 14.7 hz 010 = 22.1 hz 011 = 29.4 hz 100 = 35.3 hz (default) 101 = 44.1 hz 110 = 58.8 hz 111 = 88.2 hz 1 por = 0x90, lock = y, sw reset = y. table 64. register 0x26pwm3, pwm4 frequency 1 bit name r/w description 0 min 3 r/w when the adt7462 is in automatic fan control mode, this bit defines whether pwm3 is off (0% duty cycle) or at minimum pwm3 duty cycle when the controlling temperature is below its t min ? hysteresis value. 0 = 0% duty cycle below t min ? hysteresis (default); 1 = minimum pwm3 duty cycle below t min ? hysteresis. 1 min 4 r/w when the adt7462 is in automatic fan control mo de, this bit defines whether pwm4 is off (0% duty cycle) or at minimum pwm4 duty cycle when th e controlling temperature is below its t min ? hysteresis value. 0 = 0% duty cycle below t min ? hysteresis (default); 1 = minimum pwm4 duty cycle below t min ? hysteresis. [4:2] low freq 3 r/w these bits set the frequency of pwm3 when configured in low frequency mode. 000 = 11 hz 001 = 14.7 hz 010 = 22.1 hz 011 = 29.4 hz 100 = 35.3 hz (default) 101 = 44.1 hz 110 = 58.8 hz 111 = 88.2 hz [7:5] low freq 4 r/w these bits set the frequency of pwm4 when configured in low frequency mode. 000 = 11 hz 001 = 14.7 hz 010 = 22.1 hz 011 = 29.4 hz 100 = 35.3 hz (default) 101 = 44.1 hz 110 = 58.8 hz 111 = 88.2 hz 1 por = 0x90, lock = y, sw reset = y.
adt7462 rev. a | page 78 of 92 table 65. minimum pwmx duty cycle 1 register address r/w description por default 0x28 r/w minimum pwm1 duty cycle 0x80 0x29 r/w minimum pwm2 duty cycle 0x80 0x2a r/w minimum pwm3 duty cycle 0x80 0x2b r/w minimum pwm4 duty cycle 0x80 1 lock = y, sw reset = y. table 66. register 0x2cmaximum pwm duty cycle 1 bit name r/w description [7:0] maximum pwm duty cycle r/w this register sets the maximum % duty cycle output in automatic fan speed control mode for all four pwm outputs. 1 por = 0xc0, lock = y, sw reset = y. table 67. register 0x30thermal mask register 1 1 bit name r/w description 0 reserved r/w reserved for future use. 1 local temp r/w 1 masks alert s for an out-of-limit condition on the local temperature channel. 2 remote 1 temp r/w 1 masks alert s for an out-of-limit condition on the remote 1 temperature channel. 3 remote 2 temp r/w 1 masks alert s for an out-of-limit condition on the remote 2 temperature channel. 4 remote 3 temp r/w 1 masks alert s for an out-of-limit condition on the remote 3 temperature channel. 5 diode 1 error r/w 1 masks alert s for an open or short condition on the remote 1 channel. 6 diode 2 error r/w 1 masks alert s for an open or short condition on the remote 2 channel. 7 diode 3 error r/w 1 masks alert s for an open or short condition on the remote 3 channel. 1 por = 0x00, lock = n, sw reset = y. table 68. register 0x31thermal mask register 2 1 bit name r/w description 0 therm1 % r/w 1 masks alert s for the corresponding interrupt status bit. default = 0. 1 therm1 assert r/w 1 masks alert s for the corresponding interrupt status bit. default = 0. 2 therm1 state r/w 1 masks alert s for the corresponding interrupt status bit. default = 0. 3 therm2 % r/w 1 masks alert s for the corresponding interrupt status bit. default = 0. 4 therm2 assert r/w 1 masks alert s for the corresponding interrupt status bit. default = 0. 5 therm2 state r/w 1 masks alert s for the corresponding interrupt status bit. default = 0. 6 vrd1_assert r/w 1 masks alert s for the corresponding interrupt status bit. default = 1. 7 vrd2_assert r/w 1 masks alert s for the corresponding interrupt status bit. default = 1. 1 por = 0xc0, lock = n, sw reset = y.
adt7462 rev. a | page 79 of 92 table 69. register 0x32voltage mask register 1 1 bit name r/w description 0 +12v1 r/w 1 masks alert s for the corresponding interrupt status bit. 1 +12v2 r/w 1 masks alert s for the corresponding interrupt status bit. 2 +12v3 r/w 1 masks alert s for the corresponding interrupt status bit. 3 +3.3v r/w 1 masks alert s for the corresponding interrupt status bit. 4 pin 15 voltage r/w 1 masks alert s for the corresponding interrupt status bit. 5 pin 19 voltage r/w 1 masks alert s for the corresponding interrupt status bit. 6 +5v r/w 1 masks alert s for the corresponding interrupt status bit. 7 pin 23 voltage r/w 1 masks alert s for the corresponding interrupt status bit. 1 por = 0x00, lock = n, sw reset = y. table 70. register 0x33voltage mask register 2 1 bit name r/w description [2:0] reserved r/w reserved for future use. 3 pin 24 voltage r/w 1 masks alert s for the corresponding interrupt status bit. 4 pin 25 voltage r/w 1 masks alert s for the corresponding interrupt status bit. 5 pin 26 voltage r/w 1 masks alert s for the corresponding interrupt status bit. 6 +1.5v2 (3gio) r/w 1 masks alert s for the corresponding interrupt status bit. 7 +1.5v1 (ich) r/w 1 masks alert s for the corresponding interrupt status bit. 1 por = 0x00, lock = n, sw reset = y. table 71. register 0x34fan mask register 1 bit name r/w description 0 fan 1 fault r/w 1 masks alert s for the corresponding interrupt status bit. 1 fan 2 fault r/w 1 masks alert s for the corresponding interrupt status bit. 2 fan 3 fault r/w 1 masks alert s for the corresponding interrupt status bit. 3 fan 4 fault r/w 1 masks alert s for the corresponding interrupt status bit. 4 fan 5 fault r/w 1 masks alert s for the corresponding interrupt status bit. 5 fan 6 fault r/w 1 masks alert s for the corresponding interrupt status bit. 6 fan 7 fault r/w 1 masks alert s for the corresponding interrupt status bit. 7 fan 8 fault r/w 1 masks alert s for the corresponding interrupt status bit. 1 por = 0x00, lock = n, sw reset = y. table 72. register 0x35digital mask register 1 bit name r/w description [2:0] reserved r reserved for future use. 3 fan2max r/w 1 masks alert s for the corresponding interrupt status bit. default = 1. 4 scsi1 r/w 1 masks alert s for the corresponding interrupt status bit. default = 1. 5 scsi2 r/w 1 masks alert s for the corresponding interrupt status bit. default = 1. 6 vid comparison r/w 1 masks alert s for the corresponding interrupt status bit. default = 0. 7 chassis intrusion r/w 1 masks alert s for the corresponding interrupt status bit. default = 0. 1 por = 0x38, lock = n, sw reset = y.
adt7462 rev. a | page 80 of 92 table 73. register 0x36gpio mask register 1 bit name r/w description 0 gpio1 r/w a 1 masks alert s for the corresponding interrupt status bit. 1 gpio2 r/w a 1 masks alert s for the corresponding interrupt status bit. 2 gpio3 r/w a 1 masks alert s for the corresponding interrupt status bit. 3 gpio4 r/w a 1 masks alert s for the corresponding interrupt status bit. 4 gpio5 r/w a 1 masks alert s for the corresponding interrupt status bit. 5 gpio6 r/w a 1 masks alert s for the corresponding interrupt status bit. 6 gpio7 r/w a 1 masks alert s for the corresponding interrupt status bit. 7 gpio8 r/w a 1 masks alert s for the corresponding interrupt status bit. 1 por = 0x00, lock = n, sw reset = y. table 74. register 0x37edo 1 mask register 1 bit name r/w description 0 gpio1 r/w a 1 masks gpio1 from causing an edo1 assertion. 1 gpio2 r/w a 1 masks gpio2 from causing an edo1 assertion. 2 gpio3 r/w a 1 masks gpio3 from causing an edo1 assertion. 3 gpio4 r/w a 1 masks gpio4 from causing an edo1 assertion. 4 reserved r/w unused. 5 fan r/w a 1 masks a fan-fail conditio n from causing an edo1 assertion. 6 temp r/w a 1 masks a therm condition from causing an edo1 assertion. 7 volt r/w a 1 masks a voltage exceed limit condition from causing an edo1 assertion. 1 por = 0x00, lock = n, sw reset = y. table 75. register 0x38edo 2 mask register 1 bit name r/w description 0 gpio1 r/w a 1 masks gpio1 from causing an edo2 assertion. 1 gpio2 r/w a 1 masks gpio2 from causing an edo2 assertion. 2 gpio3 r/w a 1 masks gpio3 from causing an edo2 assertion. 3 gpio4 r/w a 1 masks gpio4 from causing an edo2 assertion. 4 reserved r/w unused. 5 fan r/w a 1 masks a fan-fail conditio n from causing an edo2 assertion. 6 temp r/w a 1 masks a therm condition from causing an edo2 assertion. 7 volt r/w a 1 masks a voltage exceed limit condition from causing an edo2 assertion. 1 por = 0x00, lock = n, sw reset = y. table 76. register 0x3ddevice id register 1 bit name r/w description [7:0] device id r this register contains the device id (0x62) for the adt7462. 1 por = 0x62, sw reset = n. table 77. register 0x3ecompany id register 1 bit name r/w description [7:0] company id r this register contains the company id (0x41) for the adt7462. 1 por = 0x41, sw reset = n.
adt7462 rev. a | page 81 of 92 table 78. register 0x3frevision register 1 bit name r/w description [7:0] revision id r this register contains the revision id (0x04) for the adt7462. 1 por = 0x04, sw reset = n. table 79. temperature limit registers 1 register address r/w description lockable por default 0x44 r/w local low temperature limit. no 0x40 0x45 r/w remote 1 low temperature/pin 15 voltage low limit. no 0x40 0x46 r/w remote 2 low temperature limit. no 0x40 0x47 r/w remote 3 low temperature/pin 19 voltage low limit. no 0x40 0x48 r/w local high temperature limit. no 0x95 0x49 r/w remote 1 high temperature/ pin 15 voltage high limit. no 0x95 0x4a r/w remote 2 high temperature limit. no 0x95 0x4b r/w remote 3 high temperatur e/pin 19 voltage high limit. no 0x95 0x4c r/w local therm1 temperature limit/+1.5v2 (3gio) voltage high limit. yes 0xa4 0x4d r/w remote 1 therm1 temperature limit. yes 0xa4 0x4e r/w remote 2 therm1 temperature limit. yes 0xa4 0x4f r/w remote 3 therm1 temperature limit. yes 0xa4 0x50 r/w local therm2 temperature limit/+1.5v1 (ich) voltage high limit. yes 0xa4 0x51 r/w remote 1 therm2 temperature limit. yes 0xa4 0x52 r/w remote 2 therm2 temperature limit. yes 0xa4 0x53 r/w remote 3 therm2 temperature limit. yes 0xa4 1 sw reset = n. table 80. register 0x54local/remote 1 temperature hysteresis 1 bit name r/w description [3:0] remote 1 hysteresis r/w these four bits set the remote 1 therm hysteresis value, 1 lsb = 1c. [7:4] local hysteresis r/w these four bits set the local therm hysteresis value, 1 lsb = 1c. 0000 = 0c 0001 = 1c 0010 = 2c 0011 = 3c 0100 = 4c (default) 0101 = 5c 0110 = 6c 0111 = 7c 1000 = 8c 1001 = 9c 1010 = 10c 1011 = 11c 1100 = 12c 1101 = 13c 1110 = 14c 1111 = 15c 1 por = 0x44, lock = y, sw reset = n.
adt7462 rev. a | page 82 of 92 table 81. register 0x55remote 2/remote 3 temperature hysteresis 1 bit name r/w description [3:0] remote 3 hysteresis r/w these four bits set the remote 3 therm hysteresis value, 1 lsb = 1c. [7:4] remote 2 hysteresis r/w these four bits set the remote 2 therm hysteresis value, 1 lsb = 1c. 0000 = 0c 0001 = 1c 0010 = 2c 0011 = 3c 0100 = 4c (default) 0101 = 5c 0110 = 6c 0111 = 7c 1000 = 8c 1001 = 9c 1010 = 10c 1011 = 11c 1100 = 12c 1101 = 13c 1110 = 14c 1111 = 15c 1 por = 0x44, lock = y, sw reset = n. table 82. offset registers 1 register address r/w description por default 0x56 r/w local offset, resolution = 0.5c. 0x00 0x57 r/w remote 1 offset, resolution = 0.5c. 0x00 0x58 r/w remote 2 offset, resolution = 0.5c. 0x00 0x59 r/w remote 3 offset, resolution = 0.5c. 0x00 1 lock = y, sw reset = n. table 83. operating point registers 1 register address r/w description por default 0x5a r/w remote 1 operating point. 0xa4 0x5b r/w remote 2 operating point. 0xa4 1 lock = y, sw reset = y. table 84. timing registers 1 register address r/w description por default 0x5c r/w local temperature t min . 0x9a 0x5d r/w remote 1 temperature t min . 0x9a 0x5e r/w remote 2 temperature t min . 0x9a 0x5f r/w remote 3 temperature t min . 0x9a 1 lock = y, sw reset = y.
adt7462 rev. a | page 83 of 92 table 85. t range /hysteresis registers 1 register address r/w description por default 0x60 r/w local t range /hysteresis 0xc4 0x61 r/w remote 1 t range /hysteresis 0xc4 0x62 r/w remote 2 t range /hysteresis 0xc4 0x63 r/w remote 3 t range /hysteresis 0xc4 1 lock = y, sw reset = y. table 86. register 0x60, register 0x61, register 0x62, re gister 0x63local, remote 1, remote 2, and remote 3 t range /hysteresis bit name r/w description [3:0] hysteresis r/w these four bits set the hysteresis in the automa tic fan speed control loop and in the dynamic t min control loop, 1 lsb = 1c. 0000 = 0c 0001 = 1c 0010 = 2c 0011 = 3c 0100 = 4c (default) 0101 = 5c 0110 = 6c 0111 = 7c 1000 = 8c 1001 = 9c 1010 = 10c 1011 = 11c 1100 = 12c 1101 = 13c 1110 = 14c 1111 = 15c [7:4] range r/w these four bits set the t range value, that is, the slope or rate of change of fan speed with respect to temperature in the automatic fan speed control loop. 0000 = 2c 0001 = 2.5c 0010 = 3.3c 0011 = 4c 0100 = 5c 0101 = 6.7c 0110 = 8c 0111 = 10c 1000 = 13.3c 1001 = 16c 1010 = 20c 1011 = 26.7c 1100 = 32c (default) 1101 = 40c 1110 = 53.3c 1111 = 80c
adt7462 rev. a | page 84 of 92 table 87. register 0x64operating point hysteresis 1 bit name r/w description [3:0] reserved r reserved for future use. [7:4] operating point hysteresis r/w these four bits set the operating point hysteresis for the dynamic t min control loop, 1 lsb = 1c. 0000 = 0c 0001 = 1c 0010 = 2c 0011 = 3c 0100 = 4c (default) 0101 = 5c 0110 = 6c 0111 = 7c 1000 = 8c 1001 = 9c 1010 = 10c 1011 = 11c 1100 = 12c 1101 = 13c 1110 = 14c 1111 = 15c 1 por = 0x40, lock = y, sw reset = y. table 88. voltage limit registers 1 register address r/w description por default 0x68 r/w +3.3v high limit. 0xff 0x69 r/w pin 23 voltage high limit. 0xff 0x6a r/w pin 24 voltage high limit. 0xff 0x6b r/w pin 25 voltage high limit. 0xff 0x6c r/w pin 26 voltage high limit. 0xff 0x6d r/w +12v1 voltage low limit. 0x00 0x6e r/w +12v2 voltage low limit. 0x00 0x6f r/w +12v3 voltage low limit. 0x00 0x70 r/w +3.3v low limit. 0x00 0x71 r/w +5v low limit. 0x00 0x72 r/w pin 23 voltage low limit. 0x20 0x73 r/w pin 24 voltage low limit. 0x00 0x74 r/w pin 25 voltage low limit. 0x00 0x75 r/w pin 26 voltage low limit. 0x80 0x76 r/w +1.5v1 (ich) voltage low limit. 0x00 0x77 r/w +1.5v2 (3gio) voltage low limit. 0x00 1 lock = n, sw reset = n.
adt7462 rev. a | page 85 of 92 table 89. tach limit registers 1 register address r/w description por default 0x78 r/w tach1 limit/vid limit. 0xff 0x79 r/w tach2 limit. 0xff 0x7a r/w tach3 limit. 0xff 0x7b r/w tach4 limit. 0xff 0x7c r/w tach5 limit/+12v1 voltage high limit. 0xff 0x7d r/w tach6 limit/+12v2 voltage high limit. 0xff 0x7e r/w tach7 limit/+5v voltage high limit. 0xff 0x7f r/w tach8 limit/+12v3 voltage high limit. 0xff 1 lock = y, sw reset = n. table 90. therm timer limit registers 1 register address r/w description por default 0x80 r/w therm1 timer limit. 0xff 0x81 r/w therm2 timer limit. 0xff 1 lock = y, sw reset = n. table 91. temperature value registers 1 register address r/w description por default 0x88 r bits [7:6] local temperature value, lsbs. 0x00 0x89 r local temperature value, msbs. 0x00 0x8a r bits [7:6] remote 1 temperature value, lsbs. 0x00 0x8b r remote 1 temperature value, msbs/pin 15 voltage. 0x00 0x8c r bits [7:6] remote 2 temperature value, lsbs. 0x00 0x8d r remote 2 temperature value, msbs. 0x00 0x8e r bits [7:6] remote 3 temperature value, lsbs. 0x00 0x8f r remote 3 temperature value, msbs/pin 19 voltage. 0x00 1 lock = n, sw reset = n. table 92. voltage value registers 1 register address r/w description por default 0x90 r pin 23 voltage value. 0x00 0x91 r pin 24 voltage value. 0x00 0x92 r pin 25 voltage value. 0x00 0x93 r pin 26 voltage value. 0x00 0x94 r +1.5v1 (ich) voltage value. 0x00 0x95 r +1.5v2 (3gio) voltage value. 0x00 0x96 r +3.3v voltage value. 0x00 1 lock = n, sw reset = n. table 93. vid value register 1 register address r/w description por default 0x97 r this register reports the st ate of the seven vid inputs. 0x00 1 lock = n, sw reset = n.
adt7462 rev. a | page 86 of 92 table 94. tach value registers 1 register address r/w description por default 0x98 r tach1, lsb. 0xff 0x99 r tach1, msb. 0xff 0x9a r tach2, lsb. 0xff 0x9b r tach2, msb. 0xff 0x9c r tach3, lsb. 0xff 0x9d r tach3, msb. 0xff 0x9e r tach4, lsb. 0xff 0x9f r tach4, msb. 0xff 0xa2 r tach5, lsb. 0xff 0xa3 r tach5, msb/+12v1 voltage value register. 0xff 0xa4 r tach6, lsb. 0xff 0xa5 r tach6, msb/+12v2 voltage value register. 0xff 0xa6 r tach7, lsb. 0xff 0xa7 r tach7, msb/+5v voltage value register. 0xff 0xa8 r tach8, lsb. 0xff 0xa9 r tach8, msb/+12v3 voltage value register. 0xff 1 lock = n, sw reset = n. table 95. pwm current duty cycle registers 1 register address r/w description por default 0xaa r/w pwm1 current duty cycle. 0x00 0xab r/w pwm2 current duty cycle. 0x00 0xac r/w pwm3 current duty cycle. 0x00 0xad r/w pwm4 current duty cycle. 0x00 1 lock = n, sw reset = n. table 96. therm timer value registers 1 register address r/w description por default 0xae r therm1 timer % on-time value. 0x00 0xaf r therm2 timer % on-time value. 0x00 1 lock = n, sw reset = n. table 97. register 0xb8host thermal status register 1 1 register 0xc0bmc thermal status register 1 2 bit name r/w description 0 reserved r reserved for future use. 1 local temp r a 1 indicates that a local temperature limit has been tripped. 2 remote 1 temp r a 1 indicates that a remote 1 temperature limit has been tripped. 3 remote 2 temp r a 1 indicates that a remote 2 temperature limit has been tripped. 4 remote 3 temp r a 1 indicates that a remote 3 temperature limit has been tripped. 5 diode 1 error r a 1 indicates that a remote 1 diode error, either an open or a short, has occurred. 6 diode 2 error r a 1 indicates that a remote 2 diode error, either an open or a short, has occurred. 7 diode 3 error r a 1 indicates that a remote 3 diode error, either an open or a short, has occurred. 1 por = 0x00, lock = n, sw reset = y. 2 por = 0x00, lock = n, sw reset = y.
adt7462 rev. a | page 87 of 92 table 98. register 0xb9host thermal status register 2 1 register 0xc1bmc thermal status register 2 1 bit name r/w description 0 therm1 % r a 1 indicates that therm1 has been asserted for longer than the programmed therm1 timer limit. 1 therm1 assert r a 1 indicates that therm1 is asserted. 2 therm1 state r a 1 indicates that a transition from high to low has taken place on the therm1 pin. 3 therm2 % r a 1 indicates that therm2 has been asserted for longer than the programmed therm2 timer limit. 4 therm2 assert r a 1 indicates that therm2 is asserted. 5 therm2 state r a 1 indicates that a transition from high to low has taken place on the therm2 pin. 6 vrd1_assert r a 1 indicates that vrd1 is asserted. 7 vrd2_assert r a 1 indicates that vrd2 is asserted. 1 por = 0x00, lock = n, sw reset = y. table 99. register 0xbahost thermal status register 3 1 bit name r/w description 0 local therm1 r a 1 indicates that the local therm1 limit has been exceeded. 1 remote 1 therm1 r a 1 indicates that the remote 1 therm1 limit has been exceeded. 2 remote 2 therm1 r a 1 indicates that the remote 2 therm1 limit has been exceeded. 3 remote 3 therm1 r a 1 indicates that the remote 3 therm1 limit has been exceeded. 4 local therm2 r a 1 indicates that the local therm2 limit has been exceeded. 5 remote 1 therm2 r a 1 indicates that the remote 1 therm2 limit has been exceeded. 6 remote 2 therm2 r a 1 indicates that the remote 2 therm2 limit has been exceeded. 7 remote 3 therm2 r a 1 indicates that the remote 3 therm2 limit has been exceeded. 1 por = 0x00, lock = n, sw reset = y. table 100. register 0xbbhost voltage status register 1 1 register 0xc3bmc voltage register 1 1 bit name r/w description 0 +12v1 r a 1 indicates that a +12v1 voltage limit has been tripped. 1 +12v2 r a 1 indicates that a +12v2 voltage limit has been tripped. 2 +12v3 r a 1 indicates that a +12v3 voltage limit has been tripped. 3 +3.3v r a 1 indicates that a +3.3v voltage limit has been tripped. 4 pin 15 voltage r a 1 indicates that a pin 15 voltage limit has been tripped. 5 pin 19 voltage r a 1 indicates that a pin 19 voltage limit has been tripped. 6 +5v r a 1 indicates that a +5v voltage limit has been tripped. 7 pin 23 voltage r a 1 indicates that a pin 23 voltage limit has been tripped. 1 por = 0x00, lock = n, sw reset = y.
adt7462 rev. a | page 88 of 92 table 101. register 0xbchost voltage status register 2 1 register 0xc4bmc voltage status register 2 1 bit name r/w description [2:0] reserved r reserved for future use. 3 pin 24 voltage r a 1 indicates that a pin 24 voltage limit has been tripped. 4 pin 25 voltage r a 1 indicates that a pin 25 voltage limit has been tripped. 5 pin 26 voltage r a 1 indicates that a pin 26 voltage limit has been tripped. 6 +1.5v2 (3gio) r a 1 indicates that a +1.5v2 (3gio) voltage limit has been tripped. 7 +1.5v1 (ich) r a 1 indicates that a +1.5v1 (ich) voltage limit has been tripped. 1 por = 0x00, lock = n, sw reset = y. table 102. register 0xbdhost fan status register 1 register 0xc5bmc fan status register 1 bit name r/w description 0 fan 1 fault r a 1 indicates a fan 1 fault. 1 fan 2 fault r a 1 indicates a fan 2 fault. 2 fan 3 fault r a 1 indicates a fan 3 fault. 3 fan 4 fault r a 1 indicates a fan 4 fault. 4 fan 5 fault r a 1 indicates a fan 5 fault. 5 fan 6 fault r a 1 indicates a fan 6 fault. 6 fan 7 fault r a 1 indicates a fan 7 fault. 7 fan 8 fault r a 1 indicates a fan 8 fault. 1 por = 0x00, lock = n, sw reset = y. table 103. register 0xbehos t digital status register 1 register 0xc6bmc digital status register 1 bit name r/w description [2:0] reserved r reserved for future use. 3 fan2max r a 1 indicates that the fan2max has been asserted as an input. 4 scsi1 r a 1 indicates that the scsi_term1 digital input has been asserted. 5 scsi2 r a 1 indicates that the scsi_term2 digital input has been asserted. 6 vid comparison r a 1 indicates a vid comparison fault. 7 chassis intrusion r a 1 indicates that the chas sis intrusion digital input has been asserted. 1 por = 0x00, lock = n, sw reset = y. table 104. register 0xbfhost gpio status register 1 bit name r/w description 0 gpio1 r/w a 1 indicates that gpio1 is asserted. 1 gpio2 r/w a 1 indicates that gpio2 is asserted. 2 gpio3 r/w a 1 indicates that gpio3 is asserted. 3 gpio4 r/w a 1 indicates that gpio4 is asserted. 4 gpio5 r/w a 1 indicates that gpio5 is asserted. 5 gpio6 r/w a 1 indicates that gpio6 is asserted. 6 gpio7 r/w a 1 indicates that gpio7 is asserted. 7 gpio8 r/w a 1 indicates that gpio8 is asserted. 1 por = 0x00, lock = n, sw reset = y.
adt7462 rev. a | page 89 of 92 outline dimensions compliant to jedec standards mo-220-vhhd-2 0.30 0.23 0.18 0.20 ref 0.80 max 0.65 typ 0.05 max 0.02 nom 12 max 1.00 0.85 0.80 seating plane coplanarity 0.08 1 32 8 9 25 24 16 17 0.50 0.40 0.30 3.50 ref 0.50 bsc pin 1 indicator top view 5.00 bsc sq 4.75 bsc sq 3.25 3.10 sq 2.95 pin 1 indicator 0.60 max 0.60 max 0.25 min exposed pad (bottom view) figure 88. 32-lead lead frame chip scale package [lfcsp_vq] 5 mm 5 mm body, very thin quad (cp-32-2) dimensions shown in millimeters ordering guide model temperature range package description package option ADT7462ACPZ-500RL7 1 ?40c to +125c 32-lead lfcsp_vq cp-32-2 adt7462acpz-reel 1 ?40c to +125c 32-lead lfcsp_vq cp-32-2 adt7462acpz-reel7 1 ?40c to +125c 32-lead lfcsp_vq cp-32-2 eval-adt7462ebz 1 evaluation board 1 z = rohs compliant part.
adt7462 rev. a | page 90 of 92 notes
adt7462 rev. a | page 91 of 92 notes
adt7462 rev. a | page 92 of 92 notes ?2006C2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d05569-0-10/07(a)

▲Up To Search▲

Price & Availability of ADT7462ACPZ-500RL7

	To Download ADT7462ACPZ-500RL7 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .